@@ 22,13 22,13 @@ 
 #include <ctl_api.h>
 #include <sam.h>
 
-#include "d2x_adc.h"
+#include "samd_adc.h"
 
 static CTL_EVENT_SET_t adc_events;
 
 #define MEASUREMENT_DONE_EVENT (1 << 0)
 
-void d2x_adc_init(uint8_t adc_no)
+void samd_adc_init(uint8_t adc_no)
 {
   adc_events = 0;
 

          
@@ 65,7 65,7 @@ void d2c_adc_shutdown(void)
   PM->APBCMASK.reg &= ~(PM_APBCMASK_ADC);
 }
 
-uint32_t d2x_adc_read_polled(uint8_t adc_no)
+uint32_t samd_adc_read_polled(uint8_t adc_no)
 {
   uint32_t r;
 

          
@@ 91,7 91,7 @@ uint32_t d2x_adc_read_polled(uint8_t adc
   return r;
 }
 
-uint32_t d2x_adc_read(uint8_t adc_no)
+uint32_t samd_adc_read(uint8_t adc_no)
 {
   unsigned wait_status;
   uint32_t r;

          
@@ 133,7 133,7 @@ uint32_t d2x_adc_read(uint8_t adc_no)
   return r;
 }
 
-int d2x_adc_set_resolution(uint16_t res)
+int samd_adc_set_resolution(uint16_t res)
 {
   if (res > 4)
   {

          

@@ 23,10 23,10 @@ 
 
 #include <stdint.h>
 
-void d2x_adc_init(uint8_t adc_no);
+void samd_adc_init(uint8_t adc_no);
 void d2c_adc_shutdown(void);
-uint32_t d2x_adc_read(uint8_t adc_no);
-uint32_t d2x_adc_read_polled(uint8_t adc_no);
+uint32_t samd_adc_read(uint8_t adc_no);
+uint32_t samd_adc_read_polled(uint8_t adc_no);
 
 /* res can be:
  *   ADC_CTRLB_RESSEL_8BIT_Val

          
@@ 34,6 34,6 @@ uint32_t d2x_adc_read_polled(uint8_t adc
  *   ADC_CTRLB_RESSEL_12BIT_Val
  *   ADC_CTRLB_RESSEL_16BIT_Val
  */
-int d2x_adc_set_resolution(uint16_t res);
+int samd_adc_set_resolution(uint16_t res);
 
 #endif /* D2X_ADC_H */
  No newline at end of file

          

@@ 25,7 25,7 @@ 
 
 #include "libtools/ctl_tools.h"
 
-enum d2x_clock_type {
+enum samd_clock_type {
   D2X_INTERNAL_32K_CLK,
   D2X_EXTERNAL_32K_CLK,
   D2X_INTERNAL_LP_32K_CLK,

          

@@ 63,7 63,7 @@ static const uint32_t eeprom_page_size_m
     0
   };
 
-int samd_get_devinfo(struct d2x_devinfo *info)
+int samd_get_devinfo(struct samd_devinfo *info)
 {
   uint32_t page_size_param;
 

          

@@ 24,7 24,7 @@ 
 #include <ctl_api.h>
 #include <stdbool.h>
 #include "samd_common.h"
-#include "d2x_eic.h"
+#include "samd_eic.h"
 
 struct interrupt_pair
 {

          
@@ 38,7 38,7 @@ static struct interrupt_pair eic_interru
 
 static bool clock_setup_done = false;
 
-int d2x_eic_setup_clock(enum d2x_clock_type clk)
+int samd_eic_setup_clock(enum d2x_clock_type clk)
 {
   uint32_t clock_source = 0;
   uint32_t clock_gen = 0;

          
@@ 110,7 110,7 @@ int d2x_eic_setup_clock(enum d2x_clock_t
   return D2X_OK;
 }
 
-int d2x_eic_init(void)
+int samd_eic_init(void)
 {
   for (uint8_t i = 0;i < EIC_INTERRUPT_AMOUNT;++i) {
     eic_interrupt_callbacks[i].fn = NULL;

          
@@ 120,7 120,7 @@ int d2x_eic_init(void)
   // EIC needs EIC bus clock (CLK_EIC_APB) and generic clock (GLCK_EIC) to be enabled
   PM->APBAMASK.reg |= PM_APBAMASK_EIC;
   if (clock_setup_done == false) {
-    d2x_eic_setup_clock(D2X_INTERNAL_8M_CLK);
+    samd_eic_setup_clock(D2X_INTERNAL_8M_CLK);
   }
 
   EIC->CTRL.bit.SWRST = 1;

          
@@ 129,7 129,7 @@ int d2x_eic_init(void)
   return D2X_OK;
 }
 
-int d2x_eic_shutdown(void)
+int samd_eic_shutdown(void)
 {
   EIC->CTRL.bit.ENABLE = 0;
   while (EIC->STATUS.bit.SYNCBUSY);

          
@@ 139,7 139,7 @@ int d2x_eic_shutdown(void)
   return D2X_OK;
 }
 
-int d2x_eic_enable(void)
+int samd_eic_enable(void)
 {
   EIC->CTRL.bit.ENABLE = 1;
   while (EIC->STATUS.bit.SYNCBUSY);

          
@@ 147,7 147,7 @@ int d2x_eic_enable(void)
   return D2X_OK;
 }
 
-int d2x_eic_disable(void)
+int samd_eic_disable(void)
 {
   EIC->CTRL.bit.ENABLE = 0;
   while (EIC->STATUS.bit.SYNCBUSY);

          
@@ 170,7 170,7 @@ static void private_set_eic_config(uint8
   EIC->CONFIG[config_num].reg = reg;
 } 
 
-int d2x_eic_enable_int(uint8_t int_no, bool filter, enum EIC_Pin_Sense sense, eic_callback_fn fn, void *user_data)
+int samd_eic_enable_int(uint8_t int_no, bool filter, enum EIC_Pin_Sense sense, eic_callback_fn fn, void *user_data)
 {
   if (int_no >= EIC_INTERRUPT_AMOUNT) {
     return D2X_FAIL;

          
@@ 197,7 197,7 @@ int d2x_eic_enable_int(uint8_t int_no, b
   return D2X_OK;
 }
 
-int d2x_eic_disable_int(uint8_t int_no)
+int samd_eic_disable_int(uint8_t int_no)
 {
   if (int_no >= EIC_INTERRUPT_AMOUNT) {
     return D2X_FAIL;

          

@@ 38,12 38,12 @@ enum EIC_Pin_Sense {
 
 typedef void (*eic_callback_fn)(uint8_t int_no, void *user_data);
 
-int d2x_eic_setup_clock(enum d2x_clock_type clk);
-int d2x_eic_init(void);
-int d2x_eic_shutdown(void);
-int d2x_eic_enable(void);
-int d2x_eic_disable(void);
-int d2x_eic_enable_int(uint8_t int_no, bool filter, enum EIC_Pin_Sense sense, eic_callback_fn fn, void *user_data);
-int d2x_eic_disable_int(uint8_t int_no);
+int samd_eic_setup_clock(enum d2x_clock_type clk);
+int samd_eic_init(void);
+int samd_eic_shutdown(void);
+int samd_eic_enable(void);
+int samd_eic_disable(void);
+int samd_eic_enable_int(uint8_t int_no, bool filter, enum EIC_Pin_Sense sense, eic_callback_fn fn, void *user_data);
+int samd_eic_disable_int(uint8_t int_no);
 
 #endif /* D2X_EIC_H */

          

@@ 20,7 20,7 @@ 
 #include <sam.h>
 
 #include "samd_common.h"
-#include "d2x_gpio.h"
+#include "samd_gpio.h"
 
 int gpio_set_input(enum SAMD2X_PORT port, uint32_t pin)
 {

          
@@ 41,7 41,7 @@ int gpio_set_output(enum SAMD2X_PORT por
 }
 
 void
-d2x_gpio_config(enum SAMD2X_PORT port, uint32_t pin, uint32_t func)
+samd_gpio_config(enum SAMD2X_PORT port, uint32_t pin, uint32_t func)
 {
   if (pin % 2 == 0) {
     PORT->Group[port].PMUX[pin / 2].bit.PMUXE = func;

          

@@ 35,7 35,7 @@ int gpio_set_input(enum SAMD2X_PORT port
 
 int gpio_set_output(enum SAMD2X_PORT port, uint32_t pin);
 
-void d2x_gpio_config(enum SAMD2X_PORT port, uint32_t pin, uint32_t func);
+void samd_gpio_config(enum SAMD2X_PORT port, uint32_t pin, uint32_t func);
 
 int gpio_set_extint(enum SAMD2X_PORT port, uint32_t pin, bool pull_up);
 

          

@@ 28,7 28,7 @@ 
 #include "samd_clocks.h"
 #include "samd_sercom.h"
 
-#include "d2x_gpio.h"
+#include "samd_gpio.h"
 
 /* Default internal oscillator speeds */
 #define I2C_REF_SPEED SystemCoreClock

          
@@ 57,11 57,11 @@ typedef struct {
   CTL_EVENT_SET_t events;
 } D21_I2C_BUS_t;
 
-CTL_STATUS_t d21_i2c_init(CTL_I2C_BUS_t *bus, unsigned speed);
+CTL_STATUS_t samd_i2c_init(CTL_I2C_BUS_t *bus, unsigned speed);
 static CTL_STATUS_t
-d21_i2c_transaction(CTL_I2C_BUS_t *super, CTL_I2C_REQUEST_t *request);
+samd_i2c_transaction(CTL_I2C_BUS_t *super, CTL_I2C_REQUEST_t *request);
 
-static CTL_STATUS_t d21_i2c_set_speed(CTL_I2C_BUS_t *super, unsigned long speed);
+static CTL_STATUS_t samd_i2c_set_speed(CTL_I2C_BUS_t *super, unsigned long speed);
 
 static void private_send_start(uint8_t sercom_no,
                                uint8_t address,

          
@@ 132,7 132,7 @@ static const struct I2C_Settings I2CS[] 
 static D21_I2C_BUS_t i2c_devices[I2C_AMOUNT];
 
 static CTL_STATUS_t
-private_d21_set_speed(uint8_t sercom_no, unsigned long speed)
+private_samd_set_speed(uint8_t sercom_no, unsigned long speed)
 {
   uint32_t baud;
   Sercom *dev = I2CS[sercom_no].dev;

          
@@ 186,7 186,7 @@ private_d21_set_speed(uint8_t sercom_no,
 }
 
 static CTL_STATUS_t
-d21_i2c_set_speed(CTL_I2C_BUS_t *super, unsigned long speed)
+samd_i2c_set_speed(CTL_I2C_BUS_t *super, unsigned long speed)
 {
   D21_I2C_BUS_t *self = (D21_I2C_BUS_t *)super;
   bool i2c_enabled;

          
@@ 202,7 202,7 @@ d21_i2c_set_speed(CTL_I2C_BUS_t *super, 
     I2C_SYNCBUSY(dev);
   }
 
-  s = private_d21_set_speed(self->sercom, speed);
+  s = private_samd_set_speed(self->sercom, speed);
 
   if (i2c_enabled) {
     dev->I2CM.CTRLA.bit.ENABLE = 1;

          
@@ 238,8 238,8 @@ private_i2c_init_master(uint8_t sercom_n
     sercom_init_clocks(sercom_no, false);
   }
 
-  d2x_gpio_config(I2CS[sercom_no].port, I2CS[sercom_no].scl_pin, I2CS[sercom_no].peripheral_func);
-  d2x_gpio_config(I2CS[sercom_no].port, I2CS[sercom_no].sda_pin, I2CS[sercom_no].peripheral_func);
+  samd_gpio_config(I2CS[sercom_no].port, I2CS[sercom_no].scl_pin, I2CS[sercom_no].peripheral_func);
+  samd_gpio_config(I2CS[sercom_no].port, I2CS[sercom_no].sda_pin, I2CS[sercom_no].peripheral_func);
 
   dev->I2CM.CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
   I2C_SYNCBUSY_SWRST(dev);

          
@@ 252,7 252,7 @@ private_i2c_init_master(uint8_t sercom_n
   dev->I2CM.CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN; // smart mode
   I2C_SYSOPBUSY(dev);
 
-  private_d21_set_speed(sercom_no, speed);
+  private_samd_set_speed(sercom_no, speed);
 
   sercom_enable_interrupt(sercom_no);
   dev->I2CM.INTENSET.reg = SERCOM_I2CM_INTFLAG_MB|SERCOM_I2CM_INTFLAG_SB|SERCOM_I2CM_INTFLAG_ERROR;

          
@@ 283,7 283,7 @@ private_i2c_init_master(uint8_t sercom_n
 }
 
 CTL_STATUS_t
-d21_i2c_init(CTL_I2C_BUS_t *super, unsigned speed)
+samd_i2c_init(CTL_I2C_BUS_t *super, unsigned speed)
 {
   uint8_t i;
   D21_I2C_BUS_t *self = (D21_I2C_BUS_t *)super;

          
@@ 300,23 300,23 @@ d21_i2c_init(CTL_I2C_BUS_t *super, unsig
 }
 
 CTL_STATUS_t
-d21_configure_i2c_bus(uint8_t bus, unsigned speed)
+samd_configure_i2c_bus(uint8_t bus, unsigned speed)
 {
   if (bus >= I2C_AMOUNT) {
     return CTL_PARAMETER_ERROR;
   }
 
   // Set up virtual functions.
-  i2c_devices[bus].core.transaction = d21_i2c_transaction;
-  i2c_devices[bus].core.set_speed = d21_i2c_set_speed;
+  i2c_devices[bus].core.transaction = samd_i2c_transaction;
+  i2c_devices[bus].core.set_speed = samd_i2c_set_speed;
   i2c_devices[bus].sercom = bus;
 
   // All done.
-  return d21_i2c_init(&i2c_devices[bus].core, speed);
+  return samd_i2c_init(&i2c_devices[bus].core, speed);
 }
 
 CTL_STATUS_t
-d21_i2c_shutdown_master(uint8_t sercom_no)
+samd_i2c_shutdown_master(uint8_t sercom_no)
 {
   if (sercom_no >= I2C_AMOUNT) {
     return CTL_PARAMETER_ERROR;

          
@@ 329,7 329,7 @@ d21_i2c_shutdown_master(uint8_t sercom_n
 }
 
 static CTL_STATUS_t
-d21_i2c_transaction(CTL_I2C_BUS_t *super, CTL_I2C_REQUEST_t *request)
+samd_i2c_transaction(CTL_I2C_BUS_t *super, CTL_I2C_REQUEST_t *request)
 {
   D21_I2C_BUS_t *self = (D21_I2C_BUS_t *)super;
   Sercom* dev = I2CS[self->sercom].dev;

          
@@ 517,7 517,7 @@ i2c_sercom_handler(D21_I2C_BUS_t *self)
 }
 
 CTL_I2C_BUS_t *
-d21_i2c_bus(uint8_t index)
+samd_i2c_bus(uint8_t index)
 {
   switch (index)
     {

          

@@ 26,14 26,14 @@ 
 #include "libtools/ctl_tools.h"
 
 CTL_I2C_BUS_t *
-d21_i2c_bus(uint8_t index);
+samd_i2c_bus(uint8_t index);
 
 CTL_STATUS_t
-d21_i2c_init(CTL_I2C_BUS_t *super, unsigned speed);
+samd_i2c_init(CTL_I2C_BUS_t *super, unsigned speed);
 
 CTL_STATUS_t
-d21_configure_i2c_bus(uint8_t bus, unsigned speed);
+samd_configure_i2c_bus(uint8_t bus, unsigned speed);
 
 CTL_STATUS_t
-d21_i2c_shutdown_master(uint8_t sercom_no);
+samd_i2c_shutdown_master(uint8_t sercom_no);
 

          

@@ 22,17 22,17 @@ 
 #include <sam.h>
 
 #include "samd_common.h"
-#include "d2x_nvm.h"
-#include "d2x_devinfo.h"
+#include "samd_nvm.h"
+#include "samd_devinfo.h"
 
 static volatile uint16_t *nvm = ((volatile uint16_t *)FLASH_ADDR);
 static uint32_t eeprom_start = 0;
 
-static struct d2x_devinfo device_info;
+static struct samd_devinfo device_info;
 
-int d2x_nvm_init(void)
+int samd_nvm_init(void)
 {
-  int status = d2x_get_devinfo(&device_info);
+  int status = samd_get_devinfo(&device_info);
 
   if (status == D2X_OK) {
     eeprom_start = (uint32_t)nvm + (device_info.flash_size - device_info.eeprom_size);

          
@@ 70,7 70,7 @@ static int nvm_clear(uint32_t address)
   return D2X_OK;
 }
 
-int d2x_eeprom_clear(uint32_t row_position)
+int samd_eeprom_clear(uint32_t row_position)
 {
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
   if (eeprom_start == 0) { // nvm init not called

          
@@ 117,7 117,7 @@ static int nvm_write(uint32_t address, u
   return D2X_OK;
 }
 
-int d2x_eeprom_write(uint32_t row_position, uint8_t *data, uint32_t data_len)
+int samd_eeprom_write(uint32_t row_position, uint8_t *data, uint32_t data_len)
 {
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
   if (nvm_address & (device_info.flash_page_size - 1)) { // invalid alignment

          
@@ 132,7 132,7 @@ int d2x_eeprom_write(uint32_t row_positi
   return nvm_write(nvm_address, data, data_len);
 }
 
-int d2x_eeprom_read(uint32_t row_position, uint8_t *data, uint32_t data_len)
+int samd_eeprom_read(uint32_t row_position, uint8_t *data, uint32_t data_len)
 {
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
 

          
@@ 153,7 153,7 @@ int d2x_eeprom_read(uint32_t row_positio
   return D2X_OK;
 }
 
-int d2x_nvm_update_aux(uint8_t bootfuse, uint8_t eeprom_fuse)
+int samd_nvm_update_aux(uint8_t bootfuse, uint8_t eeprom_fuse)
 {
   uint32_t old_fuses[2];
   uint32_t new_fuses[2];

          

@@ 32,14 32,14 @@ 
  *
  */
 
-int d2x_nvm_init(void);
+int samd_nvm_init(void);
 
-int d2x_eeprom_clear(uint32_t row_position);
+int samd_eeprom_clear(uint32_t row_position);
 
-int d2x_eeprom_write(uint32_t row_position, uint8_t *data, uint32_t data_len);
+int samd_eeprom_write(uint32_t row_position, uint8_t *data, uint32_t data_len);
 
-int d2x_eeprom_read(uint32_t row_position, uint8_t *data, uint32_t data_len);
+int samd_eeprom_read(uint32_t row_position, uint8_t *data, uint32_t data_len);
 
-int d2x_nvm_update_aux(uint8_t bootfuse, uint8_t eeprom_fuse);
+int samd_nvm_update_aux(uint8_t bootfuse, uint8_t eeprom_fuse);
 
 #endif /* D2X_NVM_H */
  No newline at end of file

          

@@ 25,13 25,13 @@ 
 
 #include "numeric_utils.h"
 
-#include "d2x_rtc.h"
+#include "samd_rtc.h"
 
 static rtc_handler_fn callback_fn;
 
 static uint32_t reference_clock = 0;
 
-void d2x_rtc_setup_clock(enum d2x_clock_type clk)
+void samd_rtc_setup_clock(enum d2x_clock_type clk)
 {
   uint32_t clock_source = 0;
   uint32_t clock_gen = 0;

          
@@ 98,13 98,13 @@ void d2x_rtc_setup_clock(enum d2x_clock_
   while (GCLK->STATUS.bit.SYNCBUSY);
 }
 
-void d2x_rtc_init(uint32_t compare_value, rtc_handler_fn callback)
+void samd_rtc_init(uint32_t compare_value, rtc_handler_fn callback)
 {
   callback_fn = callback;
 
   if (reference_clock == 0)
   {
-    d2x_rtc_setup_clock(D2X_INTERNAL_LP_32K_CLK);
+    samd_rtc_setup_clock(D2X_INTERNAL_LP_32K_CLK);
   }
 
   RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV1 | RTC_MODE0_CTRL_MATCHCLR;

          
@@ 130,7 130,7 @@ void d2x_rtc_init(uint32_t compare_value
 #endif
 }
 
-void d2x_rtc_init_ms(uint32_t sleep_time_ms, rtc_handler_fn callback)
+void samd_rtc_init_ms(uint32_t sleep_time_ms, rtc_handler_fn callback)
 {
   uint32_t counter_value;
 

          
@@ 140,13 140,13 @@ void d2x_rtc_init_ms(uint32_t sleep_time
       counter_value = (sleep_time_ms / 1000) * reference_clock;
     else
       counter_value = (reference_clock / 1000) * sleep_time_ms;
-    d2x_rtc_init(counter_value, callback);
+    samd_rtc_init(counter_value, callback);
   } else { // no overflow
-    d2x_rtc_init(counter_value/1000, callback);
+    samd_rtc_init(counter_value/1000, callback);
   }
 }
 
-void d2x_rtc_init_date(struct d2x_rtc_date *d)
+void samd_rtc_init_date(struct d2x_rtc_date *d)
 {
   // Separate clock setup.
   // Use external 32K crystal so that it generates 1Hz signal

          
@@ 172,16 172,16 @@ void d2x_rtc_init_date(struct d2x_rtc_da
   GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK4 | GCLK_CLKCTRL_ID_RTC));
   while (GCLK->STATUS.bit.SYNCBUSY);
 
-  d2x_rtc_disable();
+  samd_rtc_disable();
   RTC->MODE2.CTRL.bit.SWRST = 1;
   while (RTC->MODE2.STATUS.bit.SYNCBUSY);
 
   RTC->MODE2.CTRL.reg = RTC_MODE2_CTRL_MODE_CLOCK | RTC_MODE2_CTRL_PRESCALER_DIV1024;
   while (RTC->MODE2.STATUS.bit.SYNCBUSY);
-  d2x_rtc_set_date(d);
+  samd_rtc_set_date(d);
 }
 
-void d2x_rtc_get_date(struct d2x_rtc_date *d)
+void samd_rtc_get_date(struct d2x_rtc_date *d)
 {
   RTC_MODE2_CLOCK_Type clock_reg;
   

          
@@ 201,7 201,7 @@ void d2x_rtc_get_date(struct d2x_rtc_dat
   d->second = (clock_reg.reg & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
 }
 
-void d2x_rtc_set_date(const struct d2x_rtc_date *d)
+void samd_rtc_set_date(const struct d2x_rtc_date *d)
 {
   RTC->MODE2.CLOCK.reg = 
     RTC_MODE2_CLOCK_YEAR(d->year) |

          
@@ 213,13 213,13 @@ void d2x_rtc_set_date(const struct d2x_r
   while (RTC->MODE2.STATUS.bit.SYNCBUSY);
 }
 
-void d2x_rtc_enable(void)
+void samd_rtc_enable(void)
 {
   RTC->MODE0.CTRL.bit.ENABLE = 1;
   while (RTC->MODE0.STATUS.bit.SYNCBUSY);
 }
 
-void d2x_rtc_disable(void)
+void samd_rtc_disable(void)
 {
   RTC->MODE0.CTRL.bit.ENABLE = 0;
   while (RTC->MODE0.STATUS.bit.SYNCBUSY);

          

@@ 27,7 27,7 @@ 
 typedef void (*rtc_handler_fn)(void);
 
 
-struct d2x_rtc_date {
+struct samd_rtc_date {
   uint8_t year;
   uint8_t month;
   uint8_t day;

          
@@ 36,13 36,13 @@ struct d2x_rtc_date {
   uint8_t second;
 };
 
-void d2x_rtc_setup_clock(enum d2x_clock_type clk);
+void samd_rtc_setup_clock(enum d2x_clock_type clk);
 
-void d2x_rtc_init(uint32_t compare_value, rtc_handler_fn callback);
-void d2x_rtc_init_ms(uint32_t sleep_time_ms, rtc_handler_fn callback);
-void d2x_rtc_init_date(struct d2x_rtc_date *d);
-void d2x_rtc_get_date(struct d2x_rtc_date *d);
-void d2x_rtc_set_date(const struct d2x_rtc_date *d);
-void d2x_rtc_enable(void);
-void d2x_rtc_disable(void);
+void samd_rtc_init(uint32_t compare_value, rtc_handler_fn callback);
+void samd_rtc_init_ms(uint32_t sleep_time_ms, rtc_handler_fn callback);
+void samd_rtc_init_date(struct d2x_rtc_date *d);
+void samd_rtc_get_date(struct d2x_rtc_date *d);
+void samd_rtc_set_date(const struct d2x_rtc_date *d);
+void samd_rtc_enable(void);
+void samd_rtc_disable(void);
 

          

@@ 33,7 33,7 @@ 
 #include "samd_sercom.h"
 #include "samd_spi.h"
 
-#include "d2x_gpio.h"
+#include "samd_gpio.h"
 #include "pin_mapping.h"
 
 enum transfer_state { TRANSFER_DONE_STATE, SPI_SEND_WAIT_DRE_STATE, SPI_SEND_STATE, SPI_RECEIVE_STATE, SPI_UNKNOWN_STATE };

          
@@ 114,12 114,12 @@ static const struct SPI_Settings *SPIS =
 static uint8_t spi_bus_amount = SPI_AMOUNT;
 
 static CTL_STATUS_t
-d21_spi_enable(CTL_SPI_BUS_t *self, uint8_t cpha, uint8_t cpol, bool use_interrupts);
+samd_spi_enable(CTL_SPI_BUS_t *self, uint8_t cpha, uint8_t cpol, bool use_interrupts);
 
 static void spi_interrupt_handler(uint8_t sercom_no);
 
 void
-d21_spi_set_pin_config(const struct SPI_Settings *spi_bus_pins, uint8_t spi_amount)
+samd_spi_set_pin_config(const struct SPI_Settings *spi_bus_pins, uint8_t spi_amount)
 {
   SPIS = spi_bus_pins;
   spi_bus_amount = spi_amount;

          
@@ 129,7 129,7 @@ d21_spi_set_pin_config(const struct SPI_
 static D21_SPI_BUS_t spi_bus[SPI_MAX_AMOUNT];
 
 static void
-d21_spi_poll_exchange(CTL_SPI_BUS_t *self, const void *tx, void *rx, size_t len)
+samd_spi_poll_exchange(CTL_SPI_BUS_t *self, const void *tx, void *rx, size_t len)
 {
   D21_SPI_BUS_t *super = (D21_SPI_BUS_t*)self;
   Sercom *dev = super->spi->dev;

          
@@ 150,7 150,7 @@ d21_spi_poll_exchange(CTL_SPI_BUS_t *sel
 }
 
 static void
-d21_spi_intr_exchange(CTL_SPI_BUS_t *self, const void *tx, void *rx, size_t len)
+samd_spi_intr_exchange(CTL_SPI_BUS_t *self, const void *tx, void *rx, size_t len)
 {
   D21_SPI_BUS_t *super = (D21_SPI_BUS_t*)self;
   Sercom *dev = super->spi->dev;

          
@@ 204,7 204,7 @@ d21_spi_intr_exchange(CTL_SPI_BUS_t *sel
 
 
 static CTL_STATUS_t
-d21_spi_set_protocol(CTL_SPI_BUS_t *self)
+samd_spi_set_protocol(CTL_SPI_BUS_t *self)
 {
   uint8_t cpol = 0, cpha = 0;
   D21_SPI_BUS_t *bus = (D21_SPI_BUS_t *)self;

          
@@ 217,34 217,34 @@ d21_spi_set_protocol(CTL_SPI_BUS_t *self
   if (self->__protocol.mode & CTL_SPI_CPHA_1)
     cpha = 1;
 
-  return d21_spi_enable(self, cpha, cpol, bus->use_interrupts);
+  return samd_spi_enable(self, cpha, cpol, bus->use_interrupts);
 }
 
 CTL_SPI_BUS_t *
-d21_spi_bus(uint8_t index)
+samd_spi_bus(uint8_t index)
 {
   return &(spi_bus[index].core);
 }
 
 void
-d21_configure_spi_bus_polled(uint8_t bus_no)
+samd_configure_spi_bus_polled(uint8_t bus_no)
 {
   // Set up the SSP.
   memset(&spi_bus[bus_no], 0, sizeof(spi_bus[0]));
   spi_bus[bus_no].spi = &SPIS[bus_no];
-  spi_bus[bus_no].core.__exchange = d21_spi_poll_exchange;
-  spi_bus[bus_no].core.__set_protocol = d21_spi_set_protocol;
+  spi_bus[bus_no].core.__exchange = samd_spi_poll_exchange;
+  spi_bus[bus_no].core.__set_protocol = samd_spi_set_protocol;
   spi_bus[bus_no].use_interrupts = false;
 }
 
 void
-d21_configure_spi_bus_intr(uint8_t bus_no)
+samd_configure_spi_bus_intr(uint8_t bus_no)
 {
   // Set up the SSP.
   memset(&spi_bus[bus_no], 0, sizeof(spi_bus[0]));
   spi_bus[bus_no].spi = &SPIS[bus_no];
-  spi_bus[bus_no].core.__exchange = d21_spi_intr_exchange;
-  spi_bus[bus_no].core.__set_protocol = d21_spi_set_protocol;
+  spi_bus[bus_no].core.__exchange = samd_spi_intr_exchange;
+  spi_bus[bus_no].core.__set_protocol = samd_spi_set_protocol;
   spi_bus[bus_no].use_interrupts = true;
 }
 

          
@@ 262,7 262,7 @@ d21_configure_spi_bus_intr(uint8_t bus_n
 
 #if 0
 static void
-d2x_gpio_config(uint32_t port, uint32_t pin, uint32_t func)
+samd_gpio_config(uint32_t port, uint32_t pin, uint32_t func)
 {
   if (pin % 2 == 0) {
     PORT->Group[port].PMUX[pin / 2].bit.PMUXE = func;

          
@@ 274,7 274,7 @@ d2x_gpio_config(uint32_t port, uint32_t 
 #endif
 
 static CTL_STATUS_t
-d21_spi_enable(CTL_SPI_BUS_t *self, uint8_t cpha, uint8_t cpol, bool use_interrupts)
+samd_spi_enable(CTL_SPI_BUS_t *self, uint8_t cpha, uint8_t cpol, bool use_interrupts)
 {
   D21_SPI_BUS_t *bus = (D21_SPI_BUS_t *)self;
   Sercom *dev;

          
@@ 294,9 294,9 @@ d21_spi_enable(CTL_SPI_BUS_t *self, uint
 
   // ----------- PORT configuration ----------------
 
-  d2x_gpio_config(SPIS[sercom_no].mosi_pin.port, SPIS[sercom_no].mosi_pin.pin, SPIS[sercom_no].mosi_pin.peripheral_func);
-  d2x_gpio_config(SPIS[sercom_no].miso_pin.port, SPIS[sercom_no].miso_pin.pin, SPIS[sercom_no].miso_pin.peripheral_func);
-  d2x_gpio_config(SPIS[sercom_no].clk_pin.port, SPIS[sercom_no].clk_pin.pin, SPIS[sercom_no].clk_pin.peripheral_func);
+  samd_gpio_config(SPIS[sercom_no].mosi_pin.port, SPIS[sercom_no].mosi_pin.pin, SPIS[sercom_no].mosi_pin.peripheral_func);
+  samd_gpio_config(SPIS[sercom_no].miso_pin.port, SPIS[sercom_no].miso_pin.pin, SPIS[sercom_no].miso_pin.peripheral_func);
+  samd_gpio_config(SPIS[sercom_no].clk_pin.port, SPIS[sercom_no].clk_pin.pin, SPIS[sercom_no].clk_pin.peripheral_func);
   // SS (chip select) is controlled by software, ss is 1 by default
   gpio_set_output(SPIS[sercom_no].ss_pin.port, SPIS[sercom_no].ss_pin.pin);
   gpio_set_state(SPIS[sercom_no].ss_pin.port, SPIS[sercom_no].ss_pin.pin, true);

          
@@ 352,7 352,7 @@ d21_spi_enable(CTL_SPI_BUS_t *self, uint
 }
 
 CTL_STATUS_t
-d21_spi_disable(uint8_t sercom_no, bool use_interrupts)
+samd_spi_disable(uint8_t sercom_no, bool use_interrupts)
 {
   Sercom *dev = 0;
 

          
@@ 372,7 372,7 @@ d21_spi_disable(uint8_t sercom_no, bool 
 }
 
 CTL_STATUS_t
-d21_spi_select(uint8_t sercom_no, bool status)
+samd_spi_select(uint8_t sercom_no, bool status)
 {
   if (sercom_no >= spi_bus_amount) {
     return CTL_PARAMETER_ERROR;

          

@@ 45,21 45,21 @@ struct SPI_Settings {
 };
 
 void
-d21_spi_set_pin_config(const struct SPI_Settings *spi_bus_pins, uint8_t spi_amount);
+samd_spi_set_pin_config(const struct SPI_Settings *spi_bus_pins, uint8_t spi_amount);
 
 CTL_SPI_BUS_t *
-d21_spi_bus(uint8_t index);
+samd_spi_bus(uint8_t index);
 
 void
-d21_configure_spi_bus_polled(uint8_t bus_no);
+samd_configure_spi_bus_polled(uint8_t bus_no);
 
 void
-d21_configure_spi_bus_intr(uint8_t bus_no);
+samd_configure_spi_bus_intr(uint8_t bus_no);
 
 CTL_STATUS_t
-d21_spi_disable(uint8_t sercom_no, bool use_interrupts);
+samd_spi_disable(uint8_t sercom_no, bool use_interrupts);
 
 CTL_STATUS_t
-d21_spi_select(uint8_t index, bool status);
+samd_spi_select(uint8_t index, bool status);
 
 

          

@@ 24,8 24,8 @@ 
 
 #include <sam.h>
 
-#include "d2x_tc.h"
-#include "d2x_gpio.h"
+#include "samd_tc.h"
+#include "samd_gpio.h"
 
 #include <sam.h>
 

          
@@ 137,7 137,7 @@ static const struct Timer_Pin_Settings *
 static uint8_t tc_pin_amount = TIMER_AMOUNT;
 
 static int
-private_d2x_tc_init_16b(uint8_t timer_no, Tc *dev, uint32_t interval_in_us, uint16_t wave_gen)
+private_samd_tc_init_16b(uint8_t timer_no, Tc *dev, uint32_t interval_in_us, uint16_t wave_gen)
 {
   uint32_t clock_ctrl_id = 0;
   IRQn_Type irq_n;

          
@@ 219,7 219,7 @@ private_d2x_tc_init_16b(uint8_t timer_no
   return D2X_TC_OK;
 }
 
-int d2x_tc_clock_init(void)
+int samd_tc_clock_init(void)
 {
   GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)|GCLK_GENDIV_DIV(8);
   while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY);

          
@@ 229,7 229,7 @@ int d2x_tc_clock_init(void)
   return D2X_TC_OK;
 }
 
-int d2x_tc_init_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn)
+int samd_tc_init_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return D2X_TC_PARAMETER_ERROR;

          
@@ 239,13 239,13 @@ int d2x_tc_init_16b(uint8_t timer_no, ui
   }
 
   timer_callbacks[timer_no - TIMER_MIN_VALUE] = fn;
-  private_d2x_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
+  private_samd_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
                           (uint32_t)interval_in_us, TC_CTRLA_WAVEGEN_MFRQ_Val);
 
   return D2X_TC_OK;
 }
 
-int d2x_tc_init_output_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn)
+int samd_tc_init_output_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return D2X_TC_PARAMETER_ERROR;

          
@@ 253,22 253,22 @@ int d2x_tc_init_output_16b(uint8_t timer
 
   timer_callbacks[timer_no - TIMER_MIN_VALUE] = fn;
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.peripheral_func);
   }
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.peripheral_func);
   }
-  private_d2x_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
+  private_samd_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
                           (uint32_t)interval_in_us, TC_CTRLA_WAVEGEN_MFRQ_Val);
 
   return D2X_TC_OK;
 }
 
-int d2x_tc_init_pwm_with_prescaler_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2, uint32_t prescaler)
+int samd_tc_init_pwm_with_prescaler_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2, uint32_t prescaler)
 {
   uint32_t clock_ctrl_id = 0;
   Tc *dev;

          
@@ 312,12 312,12 @@ int d2x_tc_init_pwm_with_prescaler_8b(ui
   }
 
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.peripheral_func);
   }
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.peripheral_func);
   }

          
@@ 358,12 358,12 @@ int d2x_tc_init_pwm_with_prescaler_8b(ui
   return D2X_TC_OK;
 }
 
-int d2x_tc_init_pwm_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2)
+int samd_tc_init_pwm_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2)
 {
-  return d2x_tc_init_pwm_with_prescaler_8b(timer_no, cycle1, cycle2, 0);
+  return samd_tc_init_pwm_with_prescaler_8b(timer_no, cycle1, cycle2, 0);
 }
 
-int d2x_tc_adjust_pwm_8b(uint8_t timer_no, uint8_t signal_no, uint8_t cycle)
+int samd_tc_adjust_pwm_8b(uint8_t timer_no, uint8_t signal_no, uint8_t cycle)
 {
   Tc *dev;
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {

          
@@ 379,7 379,7 @@ int d2x_tc_adjust_pwm_8b(uint8_t timer_n
   return D2X_TC_OK;
 }
 
-int d2x_tc_init_pwm_16b(uint8_t timer_no, uint32_t cycle, timer_callback fn)
+int samd_tc_init_pwm_16b(uint8_t timer_no, uint32_t cycle, timer_callback fn)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return D2X_TC_PARAMETER_ERROR;

          
@@ 388,17 388,17 @@ int d2x_tc_init_pwm_16b(uint8_t timer_no
   timer_callbacks[timer_no - TIMER_MIN_VALUE] = fn;
 
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.peripheral_func);
   }
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.peripheral_func);
   }
 
-  private_d2x_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
+  private_samd_tc_init_16b(timer_no, timer_devs[timer_no - TIMER_MIN_VALUE],
                           cycle, TC_CTRLA_WAVEGEN_NPWM_Val);
 
   return D2X_TC_OK;

          
@@ 407,7 407,7 @@ int d2x_tc_init_pwm_16b(uint8_t timer_no
 #define ADJUSTMENT_RATIO_1 15
 #define ADJUSTMENT_RATIO_2 1
 
-int d2x_tc_init_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn)
+int samd_tc_init_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return D2X_TC_PARAMETER_ERROR;

          
@@ 416,12 416,12 @@ int d2x_tc_init_16b_ms_tick(uint8_t time
   timer_callbacks[timer_no - TIMER_MIN_VALUE] = fn;
 
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin1.peripheral_func);
   }
   if (tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.output_enabled) {
-    d2x_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
+    samd_gpio_config(tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.port,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.pin,
                     tc_pin_setup[timer_no - TIMER_MIN_VALUE].pin2.peripheral_func);
   }

          
@@ 506,7 506,7 @@ int d2x_tc_init_16b_ms_tick(uint8_t time
   return D2X_TC_OK;
 }
 
-int d2x_tc_reinit_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn)
+int samd_tc_reinit_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn)
 {
   IRQn_Type irq_n;
 

          
@@ 535,7 535,7 @@ int d2x_tc_reinit_16b_ms_tick(uint8_t ti
   while(dev->COUNT16.STATUS.bit.SYNCBUSY);
 }
 
-int d2x_tc_start(uint8_t timer_no)
+int samd_tc_start(uint8_t timer_no)
 {
   Tc *dev;
 

          
@@ 551,7 551,7 @@ int d2x_tc_start(uint8_t timer_no)
   return D2X_TC_OK;
 }
 
-int d2x_tc_stop(uint8_t timer_no)
+int samd_tc_stop(uint8_t timer_no)
 {
   Tc *dev;
 

          
@@ 567,7 567,7 @@ int d2x_tc_stop(uint8_t timer_no)
   return D2X_TC_OK;
 }
 
-int d2x_tc_forget_callback(uint8_t timer_no)
+int samd_tc_forget_callback(uint8_t timer_no)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return D2X_TC_PARAMETER_ERROR;

          
@@ 576,13 576,13 @@ int d2x_tc_forget_callback(uint8_t timer
   return D2X_TC_FAILURE;
 }
 
-void d2x_tc_set_pin_config(const struct Timer_Pin_Settings *timer_pins, uint8_t pin_amount)
+void samd_tc_set_pin_config(const struct Timer_Pin_Settings *timer_pins, uint8_t pin_amount)
 {
   tc_pin_setup = timer_pins;
   tc_pin_amount = pin_amount;
 }
 
-uint16_t d2x_tc_get_16b_count(uint8_t timer_no)
+uint16_t samd_tc_get_16b_count(uint8_t timer_no)
 {
   if (timer_no < TIMER_MIN_VALUE || timer_no >= TIMER_MIN_VALUE+TIMER_AMOUNT) {
     return 0;

          

@@ 44,24 44,24 @@ struct Timer_Pin_Settings
 
 typedef void (*timer_callback)(uint8_t mc_no);
 
-int d2x_tc_clock_init(void);
-int d2x_tc_init_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn);
-int d2x_tc_init_output_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn);
-int d2x_tc_init_pwm_16b(uint8_t timer_no, uint32_t cycle, timer_callback fn);
-int d2x_tc_init_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn);
-int d2x_tc_reinit_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn);
-int d2x_tc_init_pwm_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2);
-int d2x_tc_init_pwm_with_prescaler_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2, uint32_t prescaler);
+int samd_tc_clock_init(void);
+int samd_tc_init_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn);
+int samd_tc_init_output_16b(uint8_t timer_no, uint16_t interval_in_us, timer_callback fn);
+int samd_tc_init_pwm_16b(uint8_t timer_no, uint32_t cycle, timer_callback fn);
+int samd_tc_init_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn);
+int samd_tc_reinit_16b_ms_tick(uint8_t timer_no, uint16_t interval_in_ms, timer_callback fn);
+int samd_tc_init_pwm_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2);
+int samd_tc_init_pwm_with_prescaler_8b(uint8_t timer_no, uint8_t cycle1, uint8_t cycle2, uint32_t prescaler);
 
-int d2x_tc_adjust_pwm_8b(uint8_t timer_no, uint8_t signal_no, uint8_t cycle);
+int samd_tc_adjust_pwm_8b(uint8_t timer_no, uint8_t signal_no, uint8_t cycle);
 
-int d2x_tc_start(uint8_t timer_no);
-int d2x_tc_stop(uint8_t timer_no);
+int samd_tc_start(uint8_t timer_no);
+int samd_tc_stop(uint8_t timer_no);
 
-int d2x_tc_forget_callback(uint8_t timer_no);
+int samd_tc_forget_callback(uint8_t timer_no);
 
-void d2x_tc_set_pin_config(const struct Timer_Pin_Settings *timer_pins, uint8_t pin_amount);
+void samd_tc_set_pin_config(const struct Timer_Pin_Settings *timer_pins, uint8_t pin_amount);
 
-uint16_t d2x_tc_get_16b_count(uint8_t timer_no);
+uint16_t samd_tc_get_16b_count(uint8_t timer_no);
 
 #endif /* D2X_TC_H */
  No newline at end of file

          

@@ 23,9 23,9 @@ 
 
 #include <sam.h>
 
-#include "d2x_tc.h"
-#include "d2x_sleep.h"
-#include "d2x_gpio.h"
+#include "samd_tc.h"
+#include "samd_sleep.h"
+#include "samd_gpio.h"
 
 #define ONE_MS (SystemCoreClock / 1000)
 #define TEN_MS (SystemCoreClock / 1000 * 10)

          
@@ 54,16 54,16 @@ tick_callback(uint8_t mc_no)
 #define TIMER_NO 2
 #endif
 
-void d2x_setup_tick(void)
+void samd_setup_tick(void)
 {
-  d2x_tc_clock_init();
-  d2x_tc_init_16b_ms_tick(TIMER_NO, 10, tick_callback);
+  samd_tc_clock_init();
+  samd_tc_init_16b_ms_tick(TIMER_NO, 10, tick_callback);
   NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
-  d2x_tc_start(TIMER_NO);
+  samd_tc_start(TIMER_NO);
 }
 
 /* Idea copied from STM32 CTL sources */
-void d2x_deep_sleep(unsigned delay)
+void samd_deep_sleep(unsigned delay)
 {
   CTL_TIME_t sleep_time = 0;
   unsigned sleep_priority = 0;

          
@@ 72,14 72,14 @@ void d2x_deep_sleep(unsigned delay)
   if (delay > 10)
     {
       sleep_time = ctl_current_time;
-      d2x_tc_stop(3);
+      samd_tc_stop(3);
       ctl_global_interrupts_disable();
 
       if (delay > 4000)
         delay = 4000;
-      d2x_tc_reinit_16b_ms_tick(TIMER_NO, delay, tick_callback);
+      samd_tc_reinit_16b_ms_tick(TIMER_NO, delay, tick_callback);
 
-      d2x_tc_start(TIMER_NO);
+      samd_tc_start(TIMER_NO);
       ctl_interrupt_count = 1;
       sleep_priority = ctl_task_set_priority(ctl_task_executing, 255);
       ctl_interrupt_count = 0;

          
@@ 97,14 97,14 @@ void d2x_deep_sleep(unsigned delay)
       ctl_global_interrupts_disable();
       if (ctl_current_time == sleep_time) // something else woke us up and didn't update the time
         {
-          ctl_time_increment = d2x_tc_get_16b_count(TIMER_NO) / TICK_RATIO;
+          ctl_time_increment = samd_tc_get_16b_count(TIMER_NO) / TICK_RATIO;
           ctl_increment_tick_from_isr();
           ctl_reschedule_on_last_isr_exit = 0;
         }
-      d2x_tc_stop(TIMER_NO);
-      d2x_tc_reinit_16b_ms_tick(TIMER_NO, 10, tick_callback);
+      samd_tc_stop(TIMER_NO);
+      samd_tc_reinit_16b_ms_tick(TIMER_NO, 10, tick_callback);
       ctl_global_interrupts_enable();
-      d2x_tc_start(TIMER_NO);
+      samd_tc_start(TIMER_NO);
       ctl_task_set_priority(ctl_task_executing, sleep_priority);
     }
 }

          

@@ 21,10 21,10 @@ 
  */
 
 /* Setup timer 3 for the tick */
-void d2x_setup_tick(void);
+void samd_setup_tick(void);
 
 /* usage:
  *   unsigned d = ctl_get_sleep_delay();
- *   d2x_deep_sleep(d);
+ *   samd_deep_sleep(d);
  */
-void d2x_deep_sleep(unsigned delay);
  No newline at end of file
+void samd_deep_sleep(unsigned delay);
  No newline at end of file

          

@@ 40,7 40,7 @@ typedef struct PLATFORM_SAMD_UARTs {
   CTL_EVENT_SET_t events;
 } PLATFORM_SAMD_UARTt;
 
-static CTL_STATUS_t d21_uart_ready(CTL_UART_t *uart);
+static CTL_STATUS_t samd_uart_ready(CTL_UART_t *uart);
 static void uart_interrupt(uint8_t sercom_no);
 
 #if defined(_SAMD10_) || defined(_SAMD21_) || REV_SERCOM >= 0x200

          
@@ 116,14 116,14 @@ static const struct UART_Pin_Settings *U
 static uint8_t uart_bus_amount = UART_AMOUNT;
 
 void
-d21_uart_set_pin_config(const struct UART_Pin_Settings *uart_bus_pins, uint8_t uart_amount)
+samd_uart_set_pin_config(const struct UART_Pin_Settings *uart_bus_pins, uint8_t uart_amount)
 {
   UARTS = uart_bus_pins;
   uart_bus_amount = uart_amount;
 }
 
 static CTL_STATUS_t
-d21_uart_reconfigure(CTL_UART_t *uart)
+samd_uart_reconfigure(CTL_UART_t *uart)
 {
   PLATFORM_SAMD_UARTt *u;
   uint64_t f_ref;

          
@@ 164,8 164,8 @@ d21_uart_reconfigure(CTL_UART_t *uart)
   baud_t = 16 * 65536UL * (uint64_t)baudrate;
   baud_r = baud_t / f_ref;
   baud = 65536UL - (uint32_t)baud_r;
-  d2x_gpio_config(UARTS[uart_no].port, UARTS[uart_no].tx_pin, UARTS[uart_no].peripheral_func);
-  d2x_gpio_config(UARTS[uart_no].port, UARTS[uart_no].rx_pin, UARTS[uart_no].peripheral_func);
+  samd_gpio_config(UARTS[uart_no].port, UARTS[uart_no].tx_pin, UARTS[uart_no].peripheral_func);
+  samd_gpio_config(UARTS[uart_no].port, UARTS[uart_no].rx_pin, UARTS[uart_no].peripheral_func);
 
   // Disable UART before writing new settings
   dev->USART.CTRLA.bit.ENABLE = 0;

          
@@ 214,20 214,20 @@ d21_uart_reconfigure(CTL_UART_t *uart)
   return CTL_NO_ERROR;
 }
 
-static CTL_STATUS_t d21_uart_ready(CTL_UART_t *uart)
+static CTL_STATUS_t samd_uart_ready(CTL_UART_t *uart)
 {
   return 0;
 }
 
 static CTL_STATUS_t
-d21_uart_init(CTL_UART_t *uart)
+samd_uart_init(CTL_UART_t *uart)
 {
   PLATFORM_SAMD_UARTt *u = (PLATFORM_SAMD_UARTt*)uart;
   return uart->reconfigure(uart);
 }
 
 static CTL_STATUS_t
-d21_uart_fini(CTL_UART_t *uart)
+samd_uart_fini(CTL_UART_t *uart)
 {
   PLATFORM_SAMD_UARTt *u = (PLATFORM_SAMD_UARTt*)uart;
   u->dev->USART.INTENCLR.bit.RXC = 1;

          
@@ 241,7 241,7 @@ d21_uart_fini(CTL_UART_t *uart)
 }
 
 static inline char
-d21_uart_getc(PLATFORM_SAMD_UARTt *u)
+samd_uart_getc(PLATFORM_SAMD_UARTt *u)
 {
   char c;
   while (u->dev->USART.INTFLAG.bit.RXC == 0);

          
@@ 250,19 250,19 @@ d21_uart_getc(PLATFORM_SAMD_UARTt *u)
 }
 
 static inline void
-d21_uart_putc(PLATFORM_SAMD_UARTt *u, char c)
+samd_uart_putc(PLATFORM_SAMD_UARTt *u, char c)
 {
   while (u->dev->USART.INTFLAG.bit.DRE == 0);
   u->dev->USART.DATA.reg = (uint8_t)c;
 }
 
 static CTL_STATUS_t
-d21_uart_read_polled(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
+samd_uart_read_polled(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
 {
   char *c = rx;
 
   while (len > 0) {
-    *c++ = d21_uart_getc(u);
+    *c++ = samd_uart_getc(u);
     --len;
   }
 

          
@@ 270,7 270,7 @@ d21_uart_read_polled(PLATFORM_SAMD_UARTt
 }
 
 static CTL_STATUS_t
-d21_uart_read_intr(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
+samd_uart_read_intr(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
 {
   char *buf = rx;
   size_t n, read = 0;

          
@@ 293,17 293,17 @@ d21_uart_read_intr(PLATFORM_SAMD_UARTt *
 }
 
 static CTL_STATUS_t
-d21_uart_read(CTL_UART_t *uart, void *rx, size_t len)
+samd_uart_read(CTL_UART_t *uart, void *rx, size_t len)
 {
   if (uart->__rx) {
-    return d21_uart_read_intr((PLATFORM_SAMD_UARTt*)uart, rx, len);
+    return samd_uart_read_intr((PLATFORM_SAMD_UARTt*)uart, rx, len);
   } else {
-    return d21_uart_read_polled((PLATFORM_SAMD_UARTt*)uart, rx, len);
+    return samd_uart_read_polled((PLATFORM_SAMD_UARTt*)uart, rx, len);
   }
 }
 
 static CTL_STATUS_t
-d21_uart_write_intr(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
+samd_uart_write_intr(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
 {
   const char *c = tx;
   char t;

          
@@ 313,7 313,7 @@ d21_uart_write_intr(PLATFORM_SAMD_UARTt 
       if (!ctl_ring_buffer_empty(u->core.__tx)) {
         u->core.__idle = 0;
         t = ctl_ring_buffer_get_nb(u->core.__tx);
-        d21_uart_putc(u, t);
+        samd_uart_putc(u, t);
       } else if (u->dev->USART.INTFLAG.bit.DRE == 1) {
         u->dev->USART.INTENSET.bit.TXC = 1;
         u->core.__idle = 0;

          
@@ 331,12 331,12 @@ d21_uart_write_intr(PLATFORM_SAMD_UARTt 
 }
 
 static CTL_STATUS_t
-d21_uart_write_polled(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
+samd_uart_write_polled(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
 {
   const char *c = tx;
 
   while (len > 0) {
-    d21_uart_putc(u, *c++);
+    samd_uart_putc(u, *c++);
     --len;
   }
 

          
@@ 344,39 344,39 @@ d21_uart_write_polled(PLATFORM_SAMD_UART
 }
 
 static CTL_STATUS_t
-d21_uart_write(CTL_UART_t *uart, const void *tx, size_t len)
+samd_uart_write(CTL_UART_t *uart, const void *tx, size_t len)
 {
   if (uart->__tx) {
-    return d21_uart_write_intr((PLATFORM_SAMD_UARTt*)uart, tx, len);
+    return samd_uart_write_intr((PLATFORM_SAMD_UARTt*)uart, tx, len);
   } else {
-    return d21_uart_write_polled((PLATFORM_SAMD_UARTt*)uart, tx, len);
+    return samd_uart_write_polled((PLATFORM_SAMD_UARTt*)uart, tx, len);
   }
 }
 
-static PLATFORM_SAMD_UARTt d21_uarts[] = {
+static PLATFORM_SAMD_UARTt samd_uarts[] = {
   {
     .dev = SERCOM0,
     .uart_no = 0,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   },
   {
     .dev = SERCOM1,
     .uart_no = 1,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   },
 #if defined(_SAMD20_) || defined(_SAMD21_)
   {

          
@@ 384,63 384,63 @@ static PLATFORM_SAMD_UARTt d21_uarts[] =
     .uart_no = 2,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   },
   {
     .dev = SERCOM3,
     .uart_no = 3,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   },
   {
     .dev = SERCOM4,
     .uart_no = 4,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   },
   {
     .dev = SERCOM5,
     .uart_no = 5,
     .events = 0,
     .core.__protocol = CTL_UART_PROTOCOL_N81,
-    .core.init = d21_uart_init,
-    .core.fini = d21_uart_fini,
-    .core.read = d21_uart_read,
-    .core.write = d21_uart_write,
-    .core.ready = d21_uart_ready,
-    .core.reconfigure = d21_uart_reconfigure
+    .core.init = samd_uart_init,
+    .core.fini = samd_uart_fini,
+    .core.read = samd_uart_read,
+    .core.write = samd_uart_write,
+    .core.ready = samd_uart_ready,
+    .core.reconfigure = samd_uart_reconfigure
   }
 #endif
 };
 
 CTL_UART_t*
-d21_uart(uint8_t index)
+samd_uart(uint8_t index)
 {
   if (index < uart_bus_amount) {
-    return (CTL_UART_t*)&d21_uarts[index];
+    return (CTL_UART_t*)&samd_uarts[index];
   }
 
   return NULL;
 }
 
-static void d21_uart_intr_handler(PLATFORM_SAMD_UARTt *u)
+static void samd_uart_intr_handler(PLATFORM_SAMD_UARTt *u)
 {
   if (u->dev->USART.INTFLAG.bit.RXC) {
     ctl_ring_buffer_put_nb(u->core.__rx, u->dev->USART.DATA.reg);

          
@@ 465,7 465,7 @@ static void uart_interrupt(uint8_t serco
   ctl_enter_isr();
 
   if (sercom_no < uart_bus_amount) {
-    d21_uart_intr_handler(&d21_uarts[sercom_no]);
+    samd_uart_intr_handler(&d21_uarts[sercom_no]);
   } else {
     /* ignore silently and return immediately */
     return;

          

@@ 45,8 45,8 @@ struct UART_Pin_Settings {
 };
 
 void
-d21_uart_set_pin_config(const struct UART_Pin_Settings *uart_bus_pins, uint8_t uart_amount);
+samd_uart_set_pin_config(const struct UART_Pin_Settings *uart_bus_pins, uint8_t uart_amount);
 
-CTL_UART_t* d21_uart(uint8_t index);
+CTL_UART_t* samd_uart(uint8_t index);
 
 

          

@@ 22,11 22,11 @@ 
 
 #include <ctl_api.h>
 
-#include "d2x_wdt.h"
+#include "samd_wdt.h"
 
 static early_warn_fn ew_fn = NULL;
 
-void d2x_wdt_enable(bool window_mode, uint8_t period_cycles,
+void samd_wdt_enable(bool window_mode, uint8_t period_cycles,
                     uint8_t window_cycles, uint8_t early_warn_cycles,
                     early_warn_fn ew_handler)
 {

          
@@ 46,7 46,7 @@ void d2x_wdt_enable(bool window_mode, ui
   while(WDT->STATUS.bit.SYNCBUSY);
 }
 
-void d2x_wdt_disable(void)
+void samd_wdt_disable(void)
 {
   WDT->CTRL.bit.ENABLE = 0;
   while(WDT->STATUS.bit.SYNCBUSY);

          

@@ 31,10 31,10 @@ typedef void (*early_warn_fn)(void);
 /* Each cycle parameter takes
  * WDT_CONFIG_PER_XX_Val (like WDT_CONFIG_PER_8_Val) value
  */
-void d2x_wdt_enable(bool window_mode, uint8_t period_cycles,
+void samd_wdt_enable(bool window_mode, uint8_t period_cycles,
                     uint8_t window_cycles, uint8_t early_warn_cycles,
                     early_warn_fn ew_handler);
-void d2x_wdt_enable_2(void);
-void d2x_wdt_disable(void);
+void samd_wdt_enable_2(void);
+void samd_wdt_disable(void);
 
 #endif /* D2X_WDT_H */