@@ 57,7 57,7 @@ void samd_adc_init(uint8_t adc_no)
                    ADC_CALIB_LINEARITY_CAL((*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos));
 }
 
-void d2c_adc_shutdown(void)
+void samd_adc_shutdown(void)
 {
   ADC->INTENCLR.bit.RESRDY = 1;
   ADC->CTRLA.bit.ENABLE = 0;

          

@@ 26,10 26,10 @@ 
 #include "libtools/ctl_tools.h"
 
 enum samd_clock_type {
-  D2X_INTERNAL_32K_CLK,
-  D2X_EXTERNAL_32K_CLK,
-  D2X_INTERNAL_LP_32K_CLK,
-  D2X_INTERNAL_8M_CLK
+  SAMD_INTERNAL_32K_CLK,
+  SAMD_EXTERNAL_32K_CLK,
+  SAMD_INTERNAL_LP_32K_CLK,
+  SAMD_INTERNAL_8M_CLK
 };
 
 CTL_STATUS_t sercom_init_clocks(uint8_t sercom_no, bool use_dfll48);

          

@@ 68,7 68,7 @@ int samd_get_devinfo(struct samd_devinfo
   uint32_t page_size_param;
 
   if (info == NULL) {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   page_size_param = NVMCTRL->PARAM.bit.PSZ;

          
@@ 76,7 76,7 @@ int samd_get_devinfo(struct samd_devinfo
   if (page_size_param < sizeof(flash_page_size_mapping)) {
     info->flash_page_size = flash_page_size_mapping[page_size_param];
   } else {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   info->flash_size = NVMCTRL->PARAM.bit.NVMP * info->flash_page_size;

          
@@ 93,16 93,16 @@ int samd_get_devinfo(struct samd_devinfo
   if (eeprom_fuse < sizeof(eeprom_page_size_mapping)) {
     info->eeprom_size = eeprom_page_size_mapping[eeprom_fuse];
   } else {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   if (bootloader_fuse < sizeof(bootloader_size_mapping)) {
     info->bootloader_size = bootloader_size_mapping[bootloader_fuse];
   } else {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 void samd_get_serial(uint32_t *id0, uint32_t *id1, uint32_t *id2, uint32_t *id3)

          

@@ 25,6 25,7 @@ 
 #include <stdbool.h>
 #include "platform_samd_common.h"
 #include "platform_samd_eic.h"
+#include "platform_samd_clocks.h"
 
 struct interrupt_pair
 {

          
@@ 38,7 39,7 @@ static struct interrupt_pair eic_interru
 
 static bool clock_setup_done = false;
 
-int samd_eic_setup_clock(enum d2x_clock_type clk)
+int samd_eic_setup_clock(enum samd_clock_type clk)
 {
   uint32_t clock_source = 0;
   uint32_t clock_gen = 0;

          
@@ 46,7 47,7 @@ int samd_eic_setup_clock(enum d2x_clock_
 
   switch (clk)
   {
-    case D2X_INTERNAL_32K_CLK:
+    case SAMD_INTERNAL_32K_CLK:
       SYSCTRL->OSC32K.reg =
         SYSCTRL_OSC32K_ENABLE   |
         SYSCTRL_OSC32K_EN32K    |

          
@@ 61,7 62,7 @@ int samd_eic_setup_clock(enum d2x_clock_
       GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)|GCLK_GENDIV_DIV(1);
 
       break;
-    case D2X_EXTERNAL_32K_CLK:
+    case SAMD_EXTERNAL_32K_CLK:
       SYSCTRL->XOSC32K.reg =
         SYSCTRL_XOSC32K_XTALEN   |
         SYSCTRL_XOSC32K_EN32K    |

          
@@ 77,7 78,7 @@ int samd_eic_setup_clock(enum d2x_clock_
       GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)|GCLK_GENDIV_DIV(1);
       break;
 
-    case D2X_INTERNAL_LP_32K_CLK:
+    case SAMD_INTERNAL_LP_32K_CLK:
       clock_source = GCLK_GENCTRL_SRC_OSCULP32K;
       clock_gen = GCLK_CLKCTRL_GEN_GCLK3;
       gen_ctrl_id = GCLK_GENCTRL_ID(3);

          
@@ 85,7 86,7 @@ int samd_eic_setup_clock(enum d2x_clock_
       GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)|GCLK_GENDIV_DIV(1);
       break;
 
-    case D2X_INTERNAL_8M_CLK:
+    case SAMD_INTERNAL_8M_CLK:
       SYSCTRL->OSC8M.bit.ONDEMAND = 1;
       SYSCTRL->OSC8M.bit.RUNSTDBY = 1;
 

          
@@ 95,7 96,7 @@ int samd_eic_setup_clock(enum d2x_clock_
       break;
     
     default:
-      return D2X_FAIL;
+      return SAMD_STATUS_FAIL;
       break;
   }
 

          
@@ 107,7 108,7 @@ int samd_eic_setup_clock(enum d2x_clock_
 
   clock_setup_done = true;
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eic_init(void)

          
@@ 120,13 121,13 @@ int samd_eic_init(void)
   // EIC needs EIC bus clock (CLK_EIC_APB) and generic clock (GLCK_EIC) to be enabled
   PM->APBAMASK.reg |= PM_APBAMASK_EIC;
   if (clock_setup_done == false) {
-    samd_eic_setup_clock(D2X_INTERNAL_8M_CLK);
+    samd_eic_setup_clock(SAMD_INTERNAL_8M_CLK);
   }
 
   EIC->CTRL.bit.SWRST = 1;
   while (EIC->STATUS.bit.SYNCBUSY);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eic_shutdown(void)

          
@@ 136,7 137,7 @@ int samd_eic_shutdown(void)
 
   PM->APBAMASK.reg &= ~(PM_APBAMASK_EIC);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eic_enable(void)

          
@@ 144,7 145,7 @@ int samd_eic_enable(void)
   EIC->CTRL.bit.ENABLE = 1;
   while (EIC->STATUS.bit.SYNCBUSY);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eic_disable(void)

          
@@ 152,7 153,7 @@ int samd_eic_disable(void)
   EIC->CTRL.bit.ENABLE = 0;
   while (EIC->STATUS.bit.SYNCBUSY);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 static void private_set_eic_config(uint8_t config_num, uint8_t int_no, bool filter, enum EIC_Pin_Sense sense)

          
@@ 173,7 174,7 @@ static void private_set_eic_config(uint8
 int samd_eic_enable_int(uint8_t int_no, bool filter, enum EIC_Pin_Sense sense, eic_callback_fn fn, void *user_data)
 {
   if (int_no >= EIC_INTERRUPT_AMOUNT) {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   eic_interrupt_callbacks[int_no].fn = fn;

          
@@ 194,13 195,13 @@ int samd_eic_enable_int(uint8_t int_no, 
   ctl_set_priority(EIC_IRQn, 1);
   ctl_unmask_isr(EIC_IRQn);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eic_disable_int(uint8_t int_no)
 {
   if (int_no >= EIC_INTERRUPT_AMOUNT) {
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   ctl_mask_isr(EIC_IRQn);

          
@@ 209,7 210,7 @@ int samd_eic_disable_int(uint8_t int_no)
   eic_interrupt_callbacks[int_no].fn = NULL;
   eic_interrupt_callbacks[int_no].user_data = NULL;
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 

          

@@ 37,7 37,7 @@ enum EIC_Pin_Sense {
 
 typedef void (*eic_callback_fn)(uint8_t int_no, void *user_data);
 
-int samd_eic_setup_clock(enum d2x_clock_type clk);
+int samd_eic_setup_clock(enum samd_clock_type clk);
 int samd_eic_init(void);
 int samd_eic_shutdown(void);
 int samd_eic_enable(void);

          

@@ 28,7 28,7 @@ int gpio_set_input(enum SAMD2X_PORT port
   PORT->Group[port].DIRCLR.reg = (1 << pin);
   PORT->Group[port].PINCFG[pin].reg = PORT_PINCFG_INEN;
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int gpio_set_output(enum SAMD2X_PORT port, uint32_t pin)

          
@@ 37,7 37,7 @@ int gpio_set_output(enum SAMD2X_PORT por
   PORT->Group[port].DIRSET.reg = (1 << pin);
   PORT->Group[port].PINCFG[pin].reg = 0;
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 void

          
@@ 70,7 70,7 @@ int gpio_set_extint(enum SAMD2X_PORT por
     PORT->Group[port].PINCFG[pin].reg = PORT_PINCFG_PMUXEN|PORT_PINCFG_INEN;
   }
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 void gpio_set_state(enum SAMD2X_PORT port, uint32_t pin, bool state)

          

@@ 34,7 34,7 @@ int samd_nvm_init(void)
 {
   int status = samd_get_devinfo(&device_info);
 
-  if (status == D2X_OK) {
+  if (status == SAMD_STATUS_OK) {
     eeprom_start = (uint32_t)nvm + (device_info.flash_size - device_info.eeprom_size);
   }
 

          
@@ 45,11 45,11 @@ static int nvm_clear(uint32_t address)
 {
   if (address & (device_info.flash_page_size * NVMCTRL_ROW_PAGES - 1)) { // invalid alignment
     debug_printf("nvm_clear: invalid alignment\n");
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
   if (eeprom_start == 0) { // nvm init not called
     debug_printf("nvm_init not called\n");
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   uint32_t temp = NVMCTRL->CTRLB.reg;

          
@@ 67,14 67,14 @@ static int nvm_clear(uint32_t address)
 
   NVMCTRL->CTRLB.reg = temp; // restore cache settings
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eeprom_clear(uint32_t row_position)
 {
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
   if (eeprom_start == 0) { // nvm init not called
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   return nvm_clear(nvm_address);

          
@@ 83,7 83,7 @@ int samd_eeprom_clear(uint32_t row_posit
 static int nvm_write(uint32_t address, uint8_t *data, uint32_t data_len)
 {
   if (eeprom_start == 0) { // nvm init not called
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   while (!NVMCTRL->INTFLAG.bit.READY);

          
@@ 114,17 114,17 @@ static int nvm_write(uint32_t address, u
 
   while (!NVMCTRL->INTFLAG.bit.READY);
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_eeprom_write(uint32_t row_position, uint8_t *data, uint32_t data_len)
 {
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
   if (nvm_address & (device_info.flash_page_size - 1)) { // invalid alignment
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
   if (eeprom_start == 0) { // nvm init not called
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   debug_printf("nvm: writing to address: 0x%x (%d)\n", nvm_address, nvm_address);

          
@@ 137,7 137,7 @@ int samd_eeprom_read(uint32_t row_positi
   uint32_t nvm_address = eeprom_start + row_position * (device_info.flash_page_size * NVMCTRL_ROW_PAGES);
 
   if (eeprom_start == 0) { // nvm init not called
-    return D2X_FAIL;
+    return SAMD_STATUS_FAIL;
   }
 
   debug_printf("nvm: reading from address: 0x%x (%d)\n", nvm_address, nvm_address);

          
@@ 150,7 150,7 @@ int samd_eeprom_read(uint32_t row_positi
     }
   }
 
-  return D2X_OK;
+  return SAMD_STATUS_OK;
 }
 
 int samd_nvm_update_aux(uint8_t bootfuse, uint8_t eeprom_fuse)

          
@@ 175,12 175,12 @@ int samd_nvm_update_aux(uint8_t bootfuse
   debug_printf("new fuses: %x %x\n", new_fuses[0], new_fuses[1]);
 
   status = nvm_clear(NVMCTRL_USER);
-  if (status != D2X_OK) {
+  if (status != SAMD_STATUS_OK) {
     debug_printf("nvm_clear failed\n");
     return status;
   }
   status = nvm_write(NVMCTRL_USER, (uint8_t*)new_fuses, sizeof(new_fuses));
-  if (status != D2X_OK) {
+  if (status != SAMD_STATUS_OK) {
     debug_printf("nvm_write failed\n");
     return status;
   }

          

@@ 26,19 26,20 @@ 
 #include "numeric_utils.h"
 
 #include "platform_samd_rtc.h"
+#include "platform_samd_clocks.h"
 
 static rtc_handler_fn callback_fn;
 
 static uint32_t reference_clock = 0;
 
-void samd_rtc_setup_clock(enum d2x_clock_type clk)
+void samd_rtc_setup_clock(enum samd_clock_type clk)
 {
   uint32_t clock_source = 0;
   uint32_t clock_gen = 0;
 
   switch (clk)
   {
-    case D2X_INTERNAL_32K_CLK:
+    case SAMD_INTERNAL_32K_CLK:
       SYSCTRL->OSC32K.reg =
         SYSCTRL_OSC32K_ENABLE   |
         SYSCTRL_OSC32K_EN32K    |

          
@@ 53,7 54,7 @@ void samd_rtc_setup_clock(enum d2x_clock
       reference_clock = 8192;
 
       break;
-    case D2X_EXTERNAL_32K_CLK:
+    case SAMD_EXTERNAL_32K_CLK:
       SYSCTRL->XOSC32K.reg =
         SYSCTRL_XOSC32K_XTALEN   |
         SYSCTRL_XOSC32K_EN32K    |

          
@@ 69,7 70,7 @@ void samd_rtc_setup_clock(enum d2x_clock
       reference_clock = 8192;
       break;
 
-    case D2X_INTERNAL_LP_32K_CLK:
+    case SAMD_INTERNAL_LP_32K_CLK:
       clock_source = GCLK_GENCTRL_SRC_OSCULP32K;
       clock_gen = GCLK_CLKCTRL_GEN_GCLK4;
 

          
@@ 77,7 78,7 @@ void samd_rtc_setup_clock(enum d2x_clock
       reference_clock = 8192;
       break;
 
-    case D2X_INTERNAL_8M_CLK:
+    case SAMD_INTERNAL_8M_CLK:
       clock_source = GCLK_GENCTRL_SRC_OSC8M;
       clock_gen = GCLK_CLKCTRL_GEN_GCLK4;
 

          
@@ 104,7 105,7 @@ void samd_rtc_init(uint32_t compare_valu
 
   if (reference_clock == 0)
   {
-    samd_rtc_setup_clock(D2X_INTERNAL_LP_32K_CLK);
+    samd_rtc_setup_clock(SAMD_INTERNAL_LP_32K_CLK);
   }
 
   RTC->MODE0.CTRL.reg = RTC_MODE0_CTRL_MODE_COUNT32 | RTC_MODE0_CTRL_PRESCALER_DIV1 | RTC_MODE0_CTRL_MATCHCLR;

          
@@ 146,7 147,7 @@ void samd_rtc_init_ms(uint32_t sleep_tim
   }
 }
 
-void samd_rtc_init_date(struct d2x_rtc_date *d)
+void samd_rtc_init_date(struct samd_rtc_date *d)
 {
   // Separate clock setup.
   // Use external 32K crystal so that it generates 1Hz signal

          
@@ 181,7 182,7 @@ void samd_rtc_init_date(struct d2x_rtc_d
   samd_rtc_set_date(d);
 }
 
-void samd_rtc_get_date(struct d2x_rtc_date *d)
+void samd_rtc_get_date(struct samd_rtc_date *d)
 {
   RTC_MODE2_CLOCK_Type clock_reg;
   

          
@@ 201,7 202,7 @@ void samd_rtc_get_date(struct d2x_rtc_da
   d->second = (clock_reg.reg & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos;
 }
 
-void samd_rtc_set_date(const struct d2x_rtc_date *d)
+void samd_rtc_set_date(const struct samd_rtc_date *d)
 {
   RTC->MODE2.CLOCK.reg = 
     RTC_MODE2_CLOCK_YEAR(d->year) |

          

@@ 36,13 36,13 @@ struct samd_rtc_date {
   uint8_t second;
 };
 
-void samd_rtc_setup_clock(enum d2x_clock_type clk);
+void samd_rtc_setup_clock(enum samd_clock_type clk);
 
 void samd_rtc_init(uint32_t compare_value, rtc_handler_fn callback);
 void samd_rtc_init_ms(uint32_t sleep_time_ms, rtc_handler_fn callback);
-void samd_rtc_init_date(struct d2x_rtc_date *d);
-void samd_rtc_get_date(struct d2x_rtc_date *d);
-void samd_rtc_set_date(const struct d2x_rtc_date *d);
+void samd_rtc_init_date(struct samd_rtc_date *d);
+void samd_rtc_get_date(struct samd_rtc_date *d);
+void samd_rtc_set_date(const struct samd_rtc_date *d);
 void samd_rtc_enable(void);
 void samd_rtc_disable(void);
 

          

@@ 34,7 34,6 @@ 
 #include "platform_samd_spi.h"
 
 #include "platform_samd_gpio.h"
-#include "pin_mapping.h"
 
 enum transfer_state { TRANSFER_DONE_STATE, SPI_SEND_WAIT_DRE_STATE, SPI_SEND_STATE, SPI_RECEIVE_STATE, SPI_UNKNOWN_STATE };
 

          

@@ 38,7 38,7 @@ typedef struct PLATFORM_SAMD_UARTs {
   Sercom *dev;
   uint8_t uart_no;
   CTL_EVENT_SET_t events;
-} PLATFORM_SAMD_UARTt;
+} PLATFORM_SAMD_UART_t;
 
 static CTL_STATUS_t samd_uart_ready(CTL_UART_t *uart);
 static void uart_interrupt(uint8_t sercom_no);

          
@@ 125,7 125,7 @@ samd_uart_set_pin_config(const struct UA
 static CTL_STATUS_t
 samd_uart_reconfigure(CTL_UART_t *uart)
 {
-  PLATFORM_SAMD_UARTt *u;
+  PLATFORM_SAMD_UART_t *u;
   uint64_t f_ref;
   uint64_t baud_t;
   uint64_t baud_r;

          
@@ 140,7 140,7 @@ samd_uart_reconfigure(CTL_UART_t *uart)
     return CTL_PARAMETER_ERROR;
   }
 
-  u = (PLATFORM_SAMD_UARTt*)uart;
+  u = (PLATFORM_SAMD_UART_t*)uart;
 
   dev = u->dev;
   baudrate = u->core.__baud;

          
@@ 222,14 222,14 @@ static CTL_STATUS_t samd_uart_ready(CTL_
 static CTL_STATUS_t
 samd_uart_init(CTL_UART_t *uart)
 {
-  PLATFORM_SAMD_UARTt *u = (PLATFORM_SAMD_UARTt*)uart;
+  PLATFORM_SAMD_UART_t *u = (PLATFORM_SAMD_UART_t*)uart;
   return uart->reconfigure(uart);
 }
 
 static CTL_STATUS_t
 samd_uart_fini(CTL_UART_t *uart)
 {
-  PLATFORM_SAMD_UARTt *u = (PLATFORM_SAMD_UARTt*)uart;
+  PLATFORM_SAMD_UART_t *u = (PLATFORM_SAMD_UART_t*)uart;
   u->dev->USART.INTENCLR.bit.RXC = 1;
   u->dev->USART.INTENCLR.bit.TXC = 1;
   u->dev->USART.INTENCLR.bit.DRE = 1;

          
@@ 241,7 241,7 @@ samd_uart_fini(CTL_UART_t *uart)
 }
 
 static inline char
-samd_uart_getc(PLATFORM_SAMD_UARTt *u)
+samd_uart_getc(PLATFORM_SAMD_UART_t *u)
 {
   char c;
   while (u->dev->USART.INTFLAG.bit.RXC == 0);

          
@@ 250,14 250,14 @@ samd_uart_getc(PLATFORM_SAMD_UARTt *u)
 }
 
 static inline void
-samd_uart_putc(PLATFORM_SAMD_UARTt *u, char c)
+samd_uart_putc(PLATFORM_SAMD_UART_t *u, char c)
 {
   while (u->dev->USART.INTFLAG.bit.DRE == 0);
   u->dev->USART.DATA.reg = (uint8_t)c;
 }
 
 static CTL_STATUS_t
-samd_uart_read_polled(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
+samd_uart_read_polled(PLATFORM_SAMD_UART_t *u, void *rx, size_t len)
 {
   char *c = rx;
 

          
@@ 270,7 270,7 @@ samd_uart_read_polled(PLATFORM_SAMD_UART
 }
 
 static CTL_STATUS_t
-samd_uart_read_intr(PLATFORM_SAMD_UARTt *u, void *rx, size_t len)
+samd_uart_read_intr(PLATFORM_SAMD_UART_t *u, void *rx, size_t len)
 {
   char *buf = rx;
   size_t n, read = 0;

          
@@ 296,14 296,14 @@ static CTL_STATUS_t
 samd_uart_read(CTL_UART_t *uart, void *rx, size_t len)
 {
   if (uart->__rx) {
-    return samd_uart_read_intr((PLATFORM_SAMD_UARTt*)uart, rx, len);
+    return samd_uart_read_intr((PLATFORM_SAMD_UART_t*)uart, rx, len);
   } else {
-    return samd_uart_read_polled((PLATFORM_SAMD_UARTt*)uart, rx, len);
+    return samd_uart_read_polled((PLATFORM_SAMD_UART_t*)uart, rx, len);
   }
 }
 
 static CTL_STATUS_t
-samd_uart_write_intr(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
+samd_uart_write_intr(PLATFORM_SAMD_UART_t *u, const void *tx, size_t len)
 {
   const char *c = tx;
   char t;

          
@@ 331,7 331,7 @@ samd_uart_write_intr(PLATFORM_SAMD_UARTt
 }
 
 static CTL_STATUS_t
-samd_uart_write_polled(PLATFORM_SAMD_UARTt *u, const void *tx, size_t len)
+samd_uart_write_polled(PLATFORM_SAMD_UART_t *u, const void *tx, size_t len)
 {
   const char *c = tx;
 

          
@@ 347,13 347,13 @@ static CTL_STATUS_t
 samd_uart_write(CTL_UART_t *uart, const void *tx, size_t len)
 {
   if (uart->__tx) {
-    return samd_uart_write_intr((PLATFORM_SAMD_UARTt*)uart, tx, len);
+    return samd_uart_write_intr((PLATFORM_SAMD_UART_t*)uart, tx, len);
   } else {
-    return samd_uart_write_polled((PLATFORM_SAMD_UARTt*)uart, tx, len);
+    return samd_uart_write_polled((PLATFORM_SAMD_UART_t*)uart, tx, len);
   }
 }
 
-static PLATFORM_SAMD_UARTt samd_uarts[] = {
+static PLATFORM_SAMD_UART_t samd_uarts[] = {
   {
     .dev = SERCOM0,
     .uart_no = 0,

          
@@ 440,7 440,7 @@ samd_uart(uint8_t index)
   return NULL;
 }
 
-static void samd_uart_intr_handler(PLATFORM_SAMD_UARTt *u)
+static void samd_uart_intr_handler(PLATFORM_SAMD_UART_t *u)
 {
   if (u->dev->USART.INTFLAG.bit.RXC) {
     ctl_ring_buffer_put_nb(u->core.__rx, u->dev->USART.DATA.reg);

          
@@ 465,7 465,7 @@ static void uart_interrupt(uint8_t serco
   ctl_enter_isr();
 
   if (sercom_no < uart_bus_amount) {
-    samd_uart_intr_handler(&d21_uarts[sercom_no]);
+    samd_uart_intr_handler(&samd_uarts[sercom_no]);
   } else {
     /* ignore silently and return immediately */
     return;