# HG changeset patch # User Tero Koskinen # Date 1505547057 -10800 # Sat Sep 16 10:30:57 2017 +0300 # Node ID 3548ba7bcafd265f0b91b51b60a5d390de43ef6e # Parent df8aeafb914488f3e90444ec975f031bf87bf3b1 Use clock generator 2 for TC. Generator 3 is used by EIC, so using EIC and TC together didn't work. diff --git a/platform_samd_tc.c b/platform_samd_tc.c --- a/platform_samd_tc.c +++ b/platform_samd_tc.c @@ -180,7 +180,7 @@ } - GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); + GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); while (GCLK->STATUS.bit.SYNCBUSY); dev->COUNT16.CTRLA.bit.SWRST = 1; @@ -219,9 +219,9 @@ int samd_tc_clock_init(void) { - GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)|GCLK_GENDIV_DIV(8); + GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)|GCLK_GENDIV_DIV(8); while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY); - GCLK->GENCTRL.reg = (GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC8M | GCLK_GENCTRL_ID(3)); + GCLK->GENCTRL.reg = (GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_OSC8M | GCLK_GENCTRL_ID(2)); while (GCLK->STATUS.bit.SYNCBUSY); return D2X_TC_OK; @@ -321,7 +321,7 @@ } - GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); + GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); while (GCLK->STATUS.bit.SYNCBUSY); dev->COUNT8.CTRLA.bit.SWRST = 1; @@ -467,7 +467,7 @@ return D2X_TC_INTERNAL_ERROR; } - GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK3 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); + GCLK->CLKCTRL.reg = (uint16_t)((GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | (clock_ctrl_id << GCLK_CLKCTRL_ID_Pos))); while (GCLK->STATUS.bit.SYNCBUSY); dev->COUNT16.CTRLA.bit.SWRST = 1;