@@ 17,6 17,90 @@ 
 
 #include <pcie.h>
 
+struct pcie_cmd {
+	uint8_t padding1:2;
+	bool bus_master_enable:1;
+	uint8_t padding2:3;
+	bool parity_error_response:1;
+	bool padding3:1;
+	bool serr_enable:1;
+	bool padding4:1;
+	bool interrupt_disable:1;
+} __attribute__((packed));
+
+struct pcie_status {
+	uint8_t padding1:3;
+	bool interrupt_status:1;
+	bool capability_list:1;
+	uint8_t padding2:3;
+	bool master_data_parity_err:1;
+	uint8_t padding3:2;
+	bool signaled_target_abort:1;
+	bool received_target_abort:1;
+	bool received_master_abort:1;
+	bool system_err:1;
+	bool detected_parity_err:1;
+} __attribute__((packed));
+
+struct pcie_header {
+	uint16_t vendor_id;
+	uint16_t device_id;
+	struct pcie_cmd command;
+	struct pcie_status status;
+	uint8_t revision;
+	uint8_t prog_if;
+	uint8_t subclass;
+	uint8_t class;
+	uint16_t padding;
+	uint8_t header_type;
+	uint8_t bist;
+	uint32_t bar0;
+	uint32_t bar1;
+} __attribute__((packed));
+
+struct pcie_device {
+	struct pcie_header header;
+	uint32_t bar2;
+	uint32_t bar3;
+	uint32_t bar4;
+	uint32_t bar5;
+	uint32_t padding1;
+	uint16_t subsystem_vendor;
+	uint16_t subsystem;
+	uint32_t exp_rom_base;
+	uint8_t cap_ptr;
+	uint32_t reserved:24;
+	uint32_t reserved2;
+	uint8_t interrupt_line;
+	uint8_t interrupt_pin;
+	uint16_t padding2;
+} __attribute__((packed));
+
+struct pcie_port {
+	struct pcie_header header;
+	uint8_t primary_bus;
+	uint8_t secondary_bus;
+	uint8_t subordinate_bus;
+	uint8_t padding;
+	uint8_t io_base;
+	uint8_t io_limit;
+	struct pcie_status secondary_status;
+	uint16_t mem_base;
+	uint16_t mem_limit;
+	uint16_t prefetch_base;
+	uint16_t prefetch_limit;
+	uint32_t prefetch_base_upper;
+	uint32_t prefetch_limit_upper;
+	uint16_t io_base_upper;
+	uint16_t io_limit_upper;
+	uint8_t cap_ptr;
+	uint32_t reserved:24;
+	uint32_t exp_rom_base;
+	uint8_t interrupt_line;
+	uint8_t interrupt_pin;
+	uint16_t port_ctrl;
+} __attribute__((packed));
+
 void pcie_init(struct mcfg* mcfg) {
 
 }