Do A and F extensions

2 files changed,1004insertions(+),137deletions(-) M README.md M instructions.toml

M README.md +14 -4

@@ 56,10 56,10 @@ Possible states:Extension and state: - * **I:** WIP, version 2.1 - * **M:** WIP, version 2.0 - * **A:** Not started, version 2.1 - * **F:** Not started, version 2.2 + * **I:** Rough, version 2.1 + * **M:** Rough, version 2.0 + * **A:** WIP, version 2.1 + * **F:** WIP, version 2.2 * **D:** Not started, version 2.2 * **Q:** Not started, version 2.2 * **C:** Not started, version 2.0@@ 125,3 125,13 @@ Instruction format types* U - upper load, `op rd, imm[20]`. 1 opcode part, `opcode`. * J - Variant of J type, jump???. 1 opcode part, `opcode`. * `pseudo` -- Pseudo-instruction + + +For now, the "opcode" section in the toml just lists the text defintions +of the opcodes the standard provides, starting from least significant +bits first. Exact values can be found (in binary) in chapter 24 of the spec, +"RV32/64G Instruction Set Listings". I do kinda want to have actual hex +values for the opcodes somewhere, because it is (sometimes) useful to be +able to eyeball instructions and at least say "that's an arithmatic op" +or "this whole chunk is floating point", but the instruction format +makes it tricky.

M instructions.toml +990 -133

@@ 1087,12 1087,998 @@ corresponding signed and unsigned remainalways sign-extend the 32-bit result to 64 bits, including on a divide by zero. """ -[] -name = "" +[LR.W] +name = "Load reserved word" +opcode = "AMO / width / LR.W" +encoding = "R" +extension = "A" +long_description = """ +Complex atomic memory operations on a single memory word or doubleword are performed with the +load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address +in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that +subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address +in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the +bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and +it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a +nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates +any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only +available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd. +""" + +[LR.D] +name = "Load reserved doubleword" +opcode = "AMO / width / LR.D" +encoding = "R" +extension = "A" +long_description = """ +Complex atomic memory operations on a single memory word or doubleword are performed with the +load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address +in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that +subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address +in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the +bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and +it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a +nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates +any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only +available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd. +""" + +[SC.W] +name = "Store conditional word" +opcode = "AMO / width / SC.W" +encoding = "R" +extension = "A" +long_description = """ +Complex atomic memory operations on a single memory word or doubleword are performed with the +load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address +in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that +subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address +in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the +bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and +it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a +nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates +any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only +available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd. +""" + +[SC.D] +name = "Store conditional doubleword" +opcode = "AMO / width / SC.D" +encoding = "R" +extension = "A" +long_description = """ +Complex atomic memory operations on a single memory word or doubleword are performed with the +load-reserved (LR) and store-conditional (SC) instructions. LR.W loads a word from the address +in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that +subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address +in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the +bytes being written. If the SC.W succeeds, the instruction writes the word in rs2 to memory, and +it writes zero to rd. If the SC.W fails, the instruction does not write to memory, and it writes a +nonzero value to rd. Regardless of success or failure, executing an SC.W instruction invalidates +any reservation held by this hart. LR.D and SC.D act analogously on doublewords and are only +available on RV64. For RV64, LR.W and SC.W sign-extend the value placed in rd. +""" + + +[AMOSWAP.W] +name = "Atomic swap word" +opcode = "AMO / width / AMOSWAP.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOSWAP.D] +name = "Atomic swap doubleword" +opcode = "AMO / width / AMOSWAP.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + + +[AMOADD.W] +name = "Atomic ADD word" +opcode = "AMO / width / AMOADD.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOADD.D] +name = "Atomic ADD doubleword" +opcode = "AMO / width / AMOADD.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOAND.W] +name = "Atomic AND word" +opcode = "AMO / width / AMOAND.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOAND.D] +name = "Atomic AND doubleword" +opcode = "AMO / width / AMOAND.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOOR.W] +name = "Atomic OR word" +opcode = "AMO / width / AMOOR.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOOR.D] +name = "Atomic OR doubleword" +opcode = "AMO / width / AMOOR.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOXOR.W] +name = "Atomic XOR word" +opcode = "AMO / width / AMOXOR.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOXOR.D] +name = "Atomic XOR doubleword" +opcode = "AMO / width / AMOXOR.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMAX.W] +name = "Atomic MAX word" +opcode = "AMO / width / AMOMAX.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMAX.D] +name = "Atomic MAX doubleword" +opcode = "AMO / width / AMOMAX.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMAXU.W] +name = "Atomic MAXU word" +opcode = "AMO / width / AMOMAXU.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMAXU.D] +name = "Atomic MAXU doubleword" +opcode = "AMO / width / AMOMAXU.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMIN.W] +name = "Atomic MIN word" +opcode = "AMO / width / AMOMIN.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMIN.D] +name = "Atomic MIN doubleword" +opcode = "AMO / width / AMOMIN.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMINU.W] +name = "Atomic MINU word" +opcode = "AMO / width / AMOMINU.W" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[AMOMINU.D] +name = "Atomic MINU doubleword" +opcode = "AMO / width / AMOMINU.D" +encoding = "R" +extension = "A" +long_description = """ +The atomic memory operation (AMO) instructions perform read-modify-write operations for mul- +tiprocessor synchronization and are encoded with an R-type instruction format. These AMO in- +structions atomically load a data value from the address in rs1, place the value into register rd, +apply a binary operator to the loaded value and the original value in rs2, then store the result back +to the address in rs1. AMOs can either operate on 64-bit (RV64 only) or 32-bit words in memory. +For RV64, 32-bit AMOs always sign-extend the value placed in rd. + +The operations supported are swap, integer add, bitwise AND, bitwise OR, bitwise XOR, and +signed and unsigned integer maximum and minimum. Without ordering constraints, these AMOs +can be used to implement parallel reduction operations, where typically the return value would be +discarded by writing to x0. +""" + +[FLW] +name = "Floating point load word" +opcode = "LOAD-FP" +encoding = "I" +extension = "F" +long_description = """ +Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA, +with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads +a single-precision floating-point value from memory into floating-point register rd. FSW stores a +single-precision value from floating-point register rs2 to memory. +""" + +[FSW] +name = "Floating point store word" +opcode = "STORE-FP" +encoding = "I" +extension = "F" +long_description = """ +Floating-point loads and stores use the same base+offset addressing mode as the integer base ISA, +with a base address in register rs1 and a 12-bit signed byte offset. The FLW instruction loads +a single-precision floating-point value from memory into floating-point register rd. FSW stores a +single-precision value from floating-point register rs2 to memory. +""" + +[FADD] +name = "Floating point add" +opcode = "OP-FP / FADD" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + +[FSUB] +name = "Floating point subtract" +opcode = "OP-FP / FSUB" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FMUL] +name = "Floating point multiply" +opcode = "OP-FP / FMUL" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FDIV] +name = "Floating point divide" +opcode = "OP-FP / FDIV" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FSQRT] +name = "Floating point square root" +opcode = "OP-FP / FSQRT" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FMIN] +name = "Floating point min" +opcode = "OP-FP / FMIN" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FMAX] +name = "Floating point max" +opcode = "OP-FP / F" +encoding = "R" +extension = "F" +long_description = """ +Floating-point arithmetic instructions with one or two source operands use the R-type format with +the OP-FP major opcode. FADD.S and FMUL.S perform single-precision floating-point addition +68 +and multiplication respectively, between rs1 and rs2. FSUB.S performs the single-precision floating- +point subtraction of rs2 from rs1. FDIV.S performs the single-precision floating-point division of +rs1 by rs2. FSQRT.S computes the square root of rs1. In each case, the result is written to rd. +""" + + +[FMADD] +name = "Floating point fused multiply-add" +opcode = "FMADD" +encoding = "R4" +extension = "F" +long_description = """ +Floating-point fused multiply-add instructions require a new standard instruction format. R4-type +instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This +format is only used by the floating-point fused multiply-add instructions. +FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to +rd. FMADD.S computes (rs1×rs2)+rs3. +FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result +to rd. FMSUB.S computes (rs1×rs2)-rs3. +FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and +writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3. +FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, +and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3. +""" + +[FMSUB] +name = "Floating point fused multiply-subtract" +opcode = "FMSUB" +encoding = "R4" +extension = "F" +long_description = """ +Floating-point fused multiply-add instructions require a new standard instruction format. R4-type +instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This +format is only used by the floating-point fused multiply-add instructions. +FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to +rd. FMADD.S computes (rs1×rs2)+rs3. +FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result +to rd. FMSUB.S computes (rs1×rs2)-rs3. +FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and +writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3. +FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, +and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3. +""" + +[FNMADD] +name = "Floating point fused negate multiply-add" +opcode = "FNMADD" +encoding = "R4" +extension = "F" +long_description = """ +Floating-point fused multiply-add instructions require a new standard instruction format. R4-type +instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This +format is only used by the floating-point fused multiply-add instructions. +FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to +rd. FMADD.S computes (rs1×rs2)+rs3. +FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result +to rd. FMSUB.S computes (rs1×rs2)-rs3. +FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and +writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3. +FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, +and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3. +""" + +[FNMSUB] +name = "Floating point fused negate multiply-subtract" +opcode = "FMNSUB" +encoding = "R4" +extension = "F" +long_description = """ +Floating-point fused multiply-add instructions require a new standard instruction format. R4-type +instructions specify three source registers (rs1, rs2, and rs3) and a destination register (rd). This +format is only used by the floating-point fused multiply-add instructions. +FMADD.S multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result to +rd. FMADD.S computes (rs1×rs2)+rs3. +FMSUB.S multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final result +to rd. FMSUB.S computes (rs1×rs2)-rs3. +FNMSUB.S multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and +writes the final result to rd. FNMSUB.S computes -(rs1×rs2)+rs3. +FNMADD.S multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, +and writes the final result to rd. FNMADD.S computes -(rs1×rs2)-rs3. +""" + + + +[FCVT.W.S] +name = "Convert single floating point to word integer" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + +[FCVT.L.S] +name = "Convert single floating point to doubleword integer" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + +[FCVT.WU.S] +name = "Convert single floating point to unsigned word integer" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + +[FCVT.LU.S] +name = "Convert single floating point to unsigned doubleword integer" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + + + +[FCVT.S.W] +name = "Convert word integer to single floating point" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + + +[FCVT.S.L] +name = "Convert double word integer to single floating point" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + +[FCVT.S.WU] +name = "Convert unsigned word integer to single floating point" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + + +[FCVT.S.LU] +name = "Convert unsigned double word integer to single floating point" +opcode = "OP-FP / FCVT" +encoding = "F" +extension = "F" +long_description = """ +Floating-point-to-integer and integer-to-floating-point conversion instructions are encoded in the +OP-FP major opcode space. FCVT.W.S or FCVT.L.S converts a floating-point number in floating- +point register rs1 to a signed 32-bit or 64-bit integer, respectively, in integer register rd. FCVT.S.W +or FCVT.S.L converts a 32-bit or 64-bit signed integer, respectively, in integer register rs1 into a +floating-point number in floating-point register rd. FCVT.WU.S, FCVT.LU.S, FCVT.S.WU, and +FCVT.S.LU variants convert to or from unsigned integer values. For XLEN> 32, FCVT.W[U].S +sign-extends the 32-bit result to the destination register width. FCVT.L[U].S and FCVT.S.L[U] +are RV64-only instructions. If the rounded result is not representable in the destination format, it +is clipped to the nearest value and the invalid flag is set. Table 11.4 gives the range of valid inputs +for FCVT.int.S and the behavior for invalid inputs. + +All floating-point to integer and integer to floating-point conversion instructions round according +to the rm field. A floating-point register can be initialized to floating-point positive zero using +FCVT.S.W rd, x0, which will never set any exception flags. +""" + +[FSGNJ.S] +name = "Floating point sign injection" +opcode = "OP-FP / FSGNJ" +encoding = "R" +extension = "F" +long_description = """ +Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, +produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is +rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, +the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set +floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry +to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry +to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute +value of ry to rx (assembler pseudoinstruction FABS.S rx, ry). +""" + +[FSGNJN.S] +name = "Floating point sign injection with negation" +opcode = "OP-FP / FSGNJ" +encoding = "R" +extension = "F" +long_description = """ +Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, +produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is +rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, +the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set +floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry +to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry +to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute +value of ry to rx (assembler pseudoinstruction FABS.S rx, ry). +""" + +[FSGNJX.S] +name = "Floating point sign injection with SOR" +opcode = "OP-FP / FSGNJ" +encoding = "R" +extension = "F" +long_description = """ +Floating-point to floating-point sign-injection instructions, FSGNJ.S, FSGNJN.S, and FSGNJX.S, +produce a result that takes all bits except the sign bit from rs1. For FSGNJ, the result’s sign bit is +rs2’s sign bit; for FSGNJN, the result’s sign bit is the opposite of rs2’s sign bit; and for FSGNJX, +the sign bit is the XOR of the sign bits of rs1 and rs2. Sign-injection instructions do not set +floating-point exception flags, nor do they canonicalize NaNs. Note, FSGNJ.S rx, ry, ry moves ry +to rx (assembler pseudoinstruction FMV.S rx, ry); FSGNJN.S rx, ry, ry moves the negation of ry +to rx (assembler pseudoinstruction FNEG.S rx, ry); and FSGNJX.S rx, ry, ry moves the absolute +value of ry to rx (assembler pseudoinstruction FABS.S rx, ry). +""" + +[FMV.W.X] +name = "Move single floating point to integer register" +opcode = "OP-FP / FMV.W.X" +encoding = "R" +extension = "F" +long_description = """ +Instructions are provided to move bit patterns between the floating-point and integer registers. +FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754- +2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, +and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits +of the destination register are filled with copies of the floating-point number’s sign bit. +FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the +lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in +the transfer, and in particular, the payloads of non-canonical NaNs are preserved. +""" + +[FMV.X.W] +name = "Move word integer to single floating point register" +opcode = "OP-FP / FMV.X.W" +encoding = "R" +extension = "F" +long_description = """ +Instructions are provided to move bit patterns between the floating-point and integer registers. +FMV.X.W moves the single-precision value in floating-point register rs1 represented in IEEE 754- +2008 encoding to the lower 32 bits of integer register rd. The bits are not modified in the transfer, +and in particular, the payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits +of the destination register are filled with copies of the floating-point number’s sign bit. +FMV.W.X moves the single-precision value encoded in IEEE 754-2008 standard encoding from the +lower 32 bits of integer register rs1 to the floating-point register rd. The bits are not modified in +the transfer, and in particular, the payloads of non-canonical NaNs are preserved. +""" + +[FEQ.S] +name = "Floating point single precision equal" +opcode = "OP-FP / EQ / FCMP" +encoding = "R" +extension = "F" +long_description = """ +Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be- +tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd +if the condition holds, and 0 otherwise. +FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: +that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet +comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For +all three instructions, the result is 0 if either operand is NaN. +""" + +[FLT.S] +name = "Floating point single precision less than" +opcode = "OP-FP / LT / FCMP" +encoding = "R" +extension = "F" +long_description = """ +Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be- +tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd +if the condition holds, and 0 otherwise. +FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: +that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet +comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For +all three instructions, the result is 0 if either operand is NaN. +""" + +[FLE.S] +name = "Floating point single precision less than or equal" +opcode = "OP-FP / LE / FCMP" +encoding = "R" +extension = "F" +long_description = """ +Floating-point compare instructions (FEQ.S, FLT.S, FLE.S) perform the specified comparison be- +tween floating-point registers (rs1 = rs2, rs1 < rs2, rs1 ≤ rs2) writing 1 to the integer register rd +if the condition holds, and 0 otherwise. +FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as signaling comparisons: +that is, they set the invalid operation exception flag if either input is NaN. FEQ.S performs a quiet +comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For +all three instructions, the result is 0 if either operand is NaN. +""" + +[FCLASS.S] +name = "Floating point single precision classify" +opcode = "OP-FP / FCLASS" +encoding = "R" +extension = "F" +long_description = """ +The FCLASS.S instruction examines the value in floating-point register rs1 and writes to integer +register rd a 10-bit mask that indicates the class of the floating-point number. The format of the +mask is described in Table 11.5. The corresponding bit in rd will be set if the property is true +and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. +FCLASS.S does not set the floating-point exception flags. +""" + +[FMV.S] +name = "Copy single precision floating point register" opcode = "" -encoding = "" -extension = "" +encoding = "pseudo" +extension = "F" +long_description = """ +fsgnj.s rd, rs, rs +""" + +[FABS.S] +name = "Single precision absolute value" +opcode = "" +encoding = "pseudo" +extension = "F" +long_description = """ +fsgnjx.s rd, rs, rs +""" + +[FNEG.S] +name = "Single precision negate" +opcode = "" +encoding = "pseudo" +extension = "F" long_description = """ +fsgnjn.s rd, rs, rs +""" + +[FMV.D] +name = "Copy double precision floating point register" +opcode = "" +encoding = "pseudo" +extension = "D" +long_description = """ +fsgnj.d rd, rs, rs +""" + +[FABS.D] +name = "Double precision absolute value" +opcode = "" +encoding = "pseudo" +extension = "F" +long_description = """ +fsgnjx.d rd, rs, rs +""" + +[FNEG.D] +name = "Double precision negate" +opcode = "" +encoding = "pseudo" +extension = "F" +long_description = """ +fsgnjn.d rd, rs, rs """ []@@ 1104,132 2090,3 @@ long_description = """""" -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -[] -name = "" -opcode = "" -encoding = "" -extension = "" -long_description = """ -""" - -