@@ 4,14 4,959 @@ opcode = ""
encoding = ""
extension = "I"
description = ""
-long_description = ""
+long_description = """
+"""
+
+
+[SLTI]
+name = "Set less than immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
+similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
+XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals
+zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)
+"""
+
+
+[SLTIU]
+name = "Set less than immediate unsigned"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
+similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to
+XLEN bits then treated as an unsigned number). Note, SLTIU rd, rs1, 1 sets rd to 1 if rs1 equals
+zero, otherwise sets rd to 0 (assembler pseudoinstruction SEQZ rd, rs)
+"""
+
+[ANDI]
+name = "AND immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[ORI]
+name = "OR immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[XORI]
+name = "XOR immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
+and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs
+a bitwise logical inversion of register rs1 (assembler pseudoinstruction
+NOT rd, rs).
+"""
+
+[SLLI]
+name = "Shift left logical immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format. The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field. The rightshift
+type is encoded in bit 30. SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[SRLI]
+name = "Shift right logical immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format. The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field. The rightshift
+type is encoded in bit 30. SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[SRAI]
+name="Shift right arithmetic immediate"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Shifts by a constant are encoded as a specialization of the I-type
+format. The operand to be shiftedis inrs1, and the shift amount is
+encoded in the lower 5 bits of the I-immediate field. The rightshift
+type is encoded in bit 30. SLLI is a logical left shift (zeros are
+shifted into the lower bits); SRLI is a logical right shift (zeros are
+shifted into the upper bits); and SRAI is an arithmetic rightshift (the
+original sign bit is copied into the vacated upper bits).
+"""
+
+[LUI]
+name = "Load upper immediate"
+opcode = ""
+encoding = "U"
+extension = "I"
+description = ""
+long_description = """
+LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUIplaces the U-immediate value in the top 20 bits of the destination registerrd, filling in the lowest12 bits with zeros.
+"""
+
+[AUIPC]
+name = "Add upper immediate to PC"
+opcode = ""
+encoding = "U"
+extension = "I"
+description = ""
+long_description = """
+AUIPC (add upper immediate topc) is used to buildpc-relative addresses and uses the U-typeformat. AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits withzeros, adds this offset to the address of the AUIPC instruction, then places the result in registerrd.
+"""
+
+[ADD]
+name = "Add"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
+"""
+
+
+[SUB]
+name = "SUB"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
+"""
+
+[SLT]
+name = "Signed less than compare"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise. Note,
+SLTU rd,x0,rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs).
+"""
+
+[SLTU]
+name = "Signed less than compare unsigned"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise. Note,
+SLTU rd,x0,rs2 sets rd to 1 if rs2 is not equal to zero, otherwise sets rd to zero (assembler pseudoinstruction SNEZ rd, rs).
+"""
+
+[AND]
+name = "AND"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[OR]
+name = "OR"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[XOR]
+name = "XOR"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+AND, OR, and XOR perform bitwise logical operations.
+"""
+
+[SLL]
+name = "Shift left logical"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[SRL]
+name = "Shift right logical"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[SRA]
+name = "Shift right arithmetic"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
+"""
+
+[NOP]
+name = "No operation"
+opcode = ""
+encoding = "R"
+extension = "I"
+description = ""
+long_description = """
+The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters. NOP is encoded as ADDI x0, x0, 0.
+"""
+
+[J]
+name = "Unconditional jump"
+opcode = ""
+encoding = "J"
+extension = "I"
+description = ""
+long_description = """
+Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
+a JAL with rd=x0.
+"""
+
+[JAL]
+name = "Jump and link"
+opcode = ""
+encoding = "J"
+extension = "I"
+description = ""
+long_description = """
+The jump and link (JAL) instruction uses the J-type format, where the J-immediate encodes asigned offset in multiples of 2 bytes. The offset is sign-extended and added to the address of thejump instruction to form the jump target address. Jumps can therefore target a±1 MiB range. JAL stores the address of the instruction following the jump (pc+4) into register rd. The standard software calling convention uses x1 as the return address register and x5 as an alternate link register
+"""
+
+[JALR]
+name = "Jump and link register"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
+address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting
+the least-significant bit of the result to zero. The address of the instruction following the jump
+(pc+4) is written to register rd. Register x0 can be used as the destination if the result is not
+required.
+"""
+
+[BEQ]
+name = "Branch if equal"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+
+[BNE]
+name = "Branch if not equal"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BLT]
+name = "Branch if less than"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BLTU]
+name = "Branch if less than unsigned"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BGE]
+name = "Branch if greater or equal"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[BGEU]
+name = "Branch if greater or equal unsigned"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
+are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using
+signed and unsigned comparison respectively. BGE and BGEU take the branch if rs1 is greater
+than or equal to rs2, using signed and unsigned comparison respectively. Note, BGT, BGTU,
+BLE, and BLEU can be synthesized by reversing the operands to BLT, BLTU, BGE, and BGEU,
+respectively
+"""
+
+[LW]
+name = "Load word"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LH]
+name = "Load half word"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LHU]
+name = "Load half word unsigned"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LB]
+name = "Load byte"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+[LBU]
+name = "Load byte unsigned"
+opcode = ""
+encoding = "I"
+extension = "I"
+description = ""
+long_description = """
+The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
+then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then
+zero extends to 32-bits before storing in rd. LB and LBU are defined analogously for 8-bit values.
+"""
+
+
+[SW]
+name = "Store word"
+opcode = ""
+encoding = "S"
+extension = "I"
+description = ""
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+
+[SH]
+name = "Store half word"
+opcode = ""
+encoding = "S"
+extension = "I"
+description = ""
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+
+[SB]
+name = "Store byte"
+opcode = ""
+encoding = "S"
+extension = "I"
+description = ""
+long_description = """
+The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
+rs2 to memory
+"""
+[FENCE]
+name = "Fence"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+The FENCE instruction is used to order device I/O and memory accesses as
+viewed by other RISCV harts and external devices or coprocessors. Any
+combination of device input (I), device output (O), memory reads (R),
+and memory writes (W) may be ordered with respect to any combination of
+the same. Informally, no other RISC-V hart or external device can
+observe any operation in the successor set following a FENCE before any
+operation in the predecessor set preceding the FENCE. Chapter 14
+provides a precise description of the RISC-V memory consistency model
+"""
+
+[ECALL]
+name = "Environment call"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+The ECALL instruction is used to make a service request to the execution environment. The EEI
+will define how parameters for the service request are passed, but usually these will be in defined
+locations in the integer register file
+"""
+
+[EBREAK]
+name = "Environment break point"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+The EBREAK instruction is used to return control to a debugging environment.
+"""
+
+[HINT]
+name = "Hint"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate performance hints to the microarchitecture. HINTs are encoded as integer computational
+instructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally
+visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints.
+"""
+
+[ADDIW]
+name = "Add immediate word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1
+and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the
+result is the low 32 bits of the result sign-extended to 64 bits. Note, ADDIW rd, rs1, 0 writes
+the sign-extension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction
+SEXT.W)
+"""
+
+[SLLIW]
+name = "Shift left logical immediate word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+[SRLIW]
+name = "Shift right logical immediate word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+
+[SRAIW]
+name = "Shift right arithmetic immediate word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with
+imm[5] ̸= 0 are reserved.
+"""
+
+[ADDW]
+name = "Add word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
+but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low
+32-bits of the result is sign-extended to 64-bits and written to the destination register
+"""
+
+[SUBW]
+name = "Subtract word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
+but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low
+32-bits of the result is sign-extended to 64-bits and written to the destination register
+"""
+
+[SLLW]
+name = "Shift left logical word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[SRLW]
+name = "Shift right logical word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[SRAW]
+name = "Shift right arithmetic word"
+opcode = ""
+encoding = ""
+extension = "I"
+description = ""
+long_description = """
+SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
+on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]
+"""
+
+[LA]
+name = "Load absolute address"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Load absolute address, where delta = symbol − pc.
+
+Non-position-independent version:
+auipc rd, delta[31 : 12] + delta[11]
+addi rd, rd, delta[11:0]
+
+Position-independent version:
+auipc rd, delta[31 : 12] + delta[11]
+l{w|d} rd, rd, delta[11:0]
+
+"""
+
+[LLA]
+name = "Load local address"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Load local address, where delta = symbol − pc
+
+auipc rd, delta[31 : 12] + delta[11]
+addi rd, rd, delta[11:0]
+"""
+
+
+[LB/LH/LW/LD]
+name = "Load global byte/halfword/word/double"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Load global
+
+auipc rd, delta[31 : 12] + delta[11]
+l{b|h|w|d} rd, delta[11:0](rd)
+"""
+
+[SB/SH/SW/SD]
+name = "Store global byte/halfword/word/double"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Store global
+
+auipc rt, delta[31 : 12] + delta[11]
+s{b|h|w|d} rd, delta[11:0](rt)
+"""
+
+[LI]
+name = "Load immediate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Load immediate. Expands to "myriad sequences".
+"""
+
+[MV]
+name = "Move"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Copy register
+
+add rd, rs, 0
+"""
+
+[NOT]
+name = "One's complement negate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+One's complement negation.
+
+xori rd, rs, -1
+"""
+
+[NEG]
+name = "Two's complement negate"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Two's complement negation.
+
+sub rd, x0, rs
+"""
+
+[NEGW]
+name = "Two's complement negate word"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Two's complement negation, word length.
+
+subw rd, x0, rs
+"""
+
+
+[SEXT.W]
+name = "Sign extend word"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+Sign extend word
+
+addiw rd, rs, 0
+"""
+
+[SEQZ]
+name = "Set if equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+sltiu rd, rs, 1
+"""
+
+[SNEZ]
+name = "Set if not equal zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+sltu rd, x0, rs
+"""
+
+[SLTZ]
+name = "Set if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+slt rd, rs, x0
+"""
+
+
+[SGTZ]
+name = "Set if greater than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+lst rd, x0, rs
+"""
+
+[BEQZ]
+name = "Branch if equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+beq rs, x0, offset
+"""
+
+[BNEZ]
+name = "Branch if not equal zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bne rs, x0, offset
+"""
+
+[BLEZ]
+name = "Branch if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bge x0, rs, offset
+"""
+
+
+[BGEZ]
+name = "Branch if greater or equal to zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bge rs, x0, offset
+"""
+
+[BLTZ]
+name = "Branch if less than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+blt rs, x0, offset
+"""
+
+[BGTZ]
+name = "Branch if greater than zero"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+blt x0, rs, offset
+"""
+
+[BTG]
+name = "Branch if greater than"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+blt rt, rs, offset
+"""
+
+
+[BLE]
+name = "Branch if less than or equal"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bge rt, rs, offset
+"""
+
+[BGTU]
+name = "Branch if greater than, unsigned"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bltu rt, rs, offset
+"""
+
+[BLEU]
+name = "Branch if less than, unsigned"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+bgeu rt, rs, offset
+"""
+
+[JR]
+name = "Jump register"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+jalr x0, 0(rs)
+"""
+
+
+[RET]
+name = "Return from subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+jalr x0, 0(x1)
+"""
+
+[CALL]
+name = "Call far-away subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+auipc x1, offset[31 : 12] + offset[11]
+jalr x1, offset[11:0](x1)
+"""
+
+[TAIL]
+name = "Tail call far-away subroutine"
+opcode = ""
+encoding = "pseudo"
+extension = "I"
+description = ""
+long_description = """
+auipc x6, offset[31 : 12] + offset[11]
+jalr x0, offset[11:0](x6)
+"""
[]
name = ""
opcode = ""
encoding = ""
-extension = "I"
+extension = ""
description = ""
-long_description = ""
+long_description = """
+"""
+