# HG changeset patch # User Simon Heath # Date 1651342194 14400 # Sat Apr 30 14:09:54 2022 -0400 # Node ID 862cac7cfcadec564c7e6998d9b93c7de8f8aafb # Parent bbcaf416dff5ea05420e7bc01d1ce71aef5efad3 Ok I figured out instruction formats. diff --git a/README.md b/README.md --- a/README.md +++ b/README.md @@ -41,6 +41,9 @@ instruction set would be nice but I'm not gonna go there myself yet. RV32 is currently out of scope, but might be nice in the future. +Apparently some instruction encodings are different between RV32 and +RV64, such as SLLI, SRLI, and SRAI, so I'm not going to bother worrying +about both. Possible states: @@ -60,7 +63,7 @@ * **D:** Not started, version 2.2 * **Q:** Not started, version 2.2 * **C:** Not started, version 2.0 - * **Zicsr:** Not started, version 2.0 + * **Zicsr:** WIP, version 2.0 * **Zifencei:** Not started, version 2.0 Extensions to do later: @@ -107,8 +110,18 @@ # Instruction encoding notes - * R - register - * U - - * I - immediate - * J - jump +Instruction format types + + * R - register, `op rd, rs1, rs2`. 3 opcode parts, `opcode`, `funct3` and + `funct7` (for some gorram reason) (Oh I think that's the number of + bits in the section) + * I - immediate, `op rd, rs1, imm[12]`. 2 opcode parts, `opcode` and + `funct3`. Except on ECALL when it uses the immediate section for an + opcode, called `funct12` + * S - store, `op, rs1, rs2+imm[12]`. 2 opcode parts, `opcode` and + `funct3`. + * B - Variant of S type, probably means "branch". 2 opcode parts, + `opcode` and `funct3`. + * U - upper load, `op rd, imm[20]`. 1 opcode part, `opcode`. + * J - Variant of J type, jump???. 1 opcode part, `opcode`. * `pseudo` -- Pseudo-instruction diff --git a/instructions.toml b/instructions.toml --- a/instructions.toml +++ b/instructions.toml @@ -1,19 +1,20 @@ [ADDI] name = "Add immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / ADDI" +encoding = "I" extension = "I" -description = "" long_description = """ +ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and +the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV +rd, rs1 assembler pseudoinstruction. """ [SLTI] name = "Set less than immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / SLTI" +encoding = "I" extension = "I" -description = "" long_description = """ SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to @@ -24,10 +25,9 @@ [SLTIU] name = "Set less than immediate unsigned" -opcode = "" -encoding = "" +opcode = "OP-IMM / SLTIU" +encoding = "I" extension = "I" -description = "" long_description = """ SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to @@ -37,10 +37,9 @@ [ANDI] name = "AND immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / ANDI" +encoding = "I" extension = "I" -description = "" long_description = """ ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs @@ -50,10 +49,9 @@ [ORI] name = "OR immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / " +encoding = "I" extension = "I" -description = "" long_description = """ ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs @@ -63,10 +61,9 @@ [XORI] name = "XOR immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / " +encoding = "I" extension = "I" -description = "" long_description = """ ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs @@ -76,10 +73,8 @@ [SLLI] name = "Shift left logical immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / SLLI" extension = "I" -description = "" long_description = """ Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shiftedis inrs1, and the shift amount is @@ -92,10 +87,9 @@ [SRLI] name = "Shift right logical immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / SRLI" +encoding = "I" extension = "I" -description = "" long_description = """ Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shiftedis inrs1, and the shift amount is @@ -108,10 +102,9 @@ [SRAI] name="Shift right arithmetic immediate" -opcode = "" -encoding = "" +opcode = "OP-IMM / SRAI" +encoding = "I" extension = "I" -description = "" long_description = """ Shifts by a constant are encoded as a specialization of the I-type format. The operand to be shiftedis inrs1, and the shift amount is @@ -124,30 +117,27 @@ [LUI] name = "Load upper immediate" -opcode = "" +opcode = "LUI" encoding = "U" extension = "I" -description = "" long_description = """ LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUIplaces the U-immediate value in the top 20 bits of the destination registerrd, filling in the lowest12 bits with zeros. """ [AUIPC] name = "Add upper immediate to PC" -opcode = "" +opcode = "AUIPC" encoding = "U" extension = "I" -description = "" long_description = """ AUIPC (add upper immediate topc) is used to buildpc-relative addresses and uses the U-typeformat. AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits withzeros, adds this offset to the address of the AUIPC instruction, then places the result in registerrd. """ [ADD] name = "Add" -opcode = "" +opcode = "OP / " encoding = "R" extension = "I" -description = "" long_description = """ ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd. """ @@ -155,20 +145,18 @@ [SUB] name = "SUB" -opcode = "" +opcode = "OP / " encoding = "R" extension = "I" -description = "" long_description = """ ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd. """ [SLT] name = "Signed less than compare" -opcode = "" +opcode = "OP / " encoding = "R" extension = "I" -description = "" long_description = """ SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1