~icefox/riscv-reference commit

2 files changed, 171 insertions(+), 219 deletions(-)

M README.md
M instructions.toml

M README.md +18 -5

@@ 41,6 41,9 @@ probably be a new one along soon.  Anoth
 instruction set would be nice but I'm not gonna go there myself yet.
 
 RV32 is currently out of scope, but might be nice in the future.
+Apparently some instruction encodings are different between RV32 and
+RV64, such as SLLI, SRLI, and SRAI, so I'm not going to bother worrying
+about both.
 
 Possible states:
 

          
@@ 60,7 63,7 @@ Extension and state:
  * **D:** Not started, version 2.2
  * **Q:** Not started, version 2.2
  * **C:** Not started, version 2.0
- * **Zicsr:** Not started, version 2.0
+ * **Zicsr:** WIP, version 2.0
  * **Zifencei:** Not started, version 2.0
 
 Extensions to do later:

          
@@ 107,8 110,18 @@ Other guilty instructions: `fence`, `jal
 
 # Instruction encoding notes
 
- * R - register
- * U -
- * I - immediate
- * J - jump
+Instruction format types
+
+ * R - register, `op rd, rs1, rs2`.  3 opcode parts, `opcode`, `funct3` and
+   `funct7` (for some gorram reason) (Oh I think that's the number of
+   bits in the section)
+ * I - immediate, `op rd, rs1, imm[12]`.  2 opcode parts, `opcode` and
+   `funct3`.  Except on ECALL when it uses the immediate section for an
+   opcode, called `funct12`
+ * S - store, `op, rs1, rs2+imm[12]`.  2 opcode parts, `opcode` and
+   `funct3`.
+ * B - Variant of S type, probably means "branch".  2 opcode parts,
+   `opcode` and `funct3`.
+ * U - upper load, `op rd, imm[20]`.  1 opcode part, `opcode`.
+ * J - Variant of J type, jump???.  1 opcode part, `opcode`.
  * `pseudo` -- Pseudo-instruction

M instructions.toml +153 -214

@@ 1,19 1,20 @@ 
 [ADDI]
 name = "Add immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / ADDI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
+ADDI adds the sign-extended 12-bit immediate to register rs1. Arithmetic overflow is ignored and
+the result is simply the low XLEN bits of the result. ADDI rd, rs1, 0 is used to implement the MV
+rd, rs1 assembler pseudoinstruction.
 """
 
 
 [SLTI]
 name = "Set less than immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / SLTI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
 similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to

          
@@ 24,10 25,9 @@ zero, otherwise sets rd to 0 (assembler 
 
 [SLTIU]
 name = "Set less than immediate unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / SLTIU"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 SLTI (set less than immediate) places the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. SLTIU is
 similar but compares the values as unsigned numbers (i.e., the immediate is first sign-extended to

          
@@ 37,10 37,9 @@ zero, otherwise sets rd to 0 (assembler 
 
 [ANDI]
 name = "AND immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / ANDI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs

          
@@ 50,10 49,9 @@ NOT rd, rs).
 
 [ORI]
 name = "OR immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / "
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs

          
@@ 63,10 61,9 @@ NOT rd, rs).
 
 [XORI]
 name = "XOR immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / "
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 ANDI, ORI, XORI are logical operations that perform bitwise AND, OR, and XOR on register rs1
 and the sign-extended 12-bit immediate and place the result in rd. Note, XORI rd, rs1, -1 performs

          
@@ 76,10 73,8 @@ NOT rd, rs).
 
 [SLLI]
 name = "Shift left logical immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / SLLI"
 extension = "I"
-description = ""
 long_description = """
 Shifts by a constant are encoded as a specialization of the I-type
 format.  The operand to be shiftedis inrs1, and the shift amount is

          
@@ 92,10 87,9 @@ original sign bit is copied into the vac
 
 [SRLI]
 name = "Shift right logical immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / SRLI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 Shifts by a constant are encoded as a specialization of the I-type
 format.  The operand to be shiftedis inrs1, and the shift amount is

          
@@ 108,10 102,9 @@ original sign bit is copied into the vac
 
 [SRAI]
 name="Shift right arithmetic immediate"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM / SRAI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 Shifts by a constant are encoded as a specialization of the I-type
 format.  The operand to be shiftedis inrs1, and the shift amount is

          
@@ 124,30 117,27 @@ original sign bit is copied into the vac
 
 [LUI]
 name = "Load upper immediate"
-opcode = ""
+opcode = "LUI"
 encoding = "U"
 extension = "I"
-description = ""
 long_description = """
 LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format.  LUIplaces the U-immediate value in the top 20 bits of the destination registerrd, filling in the lowest12 bits with zeros.
 """
 
 [AUIPC]
 name = "Add upper immediate to PC"
-opcode = ""
+opcode = "AUIPC"
 encoding = "U"
 extension = "I"
-description = ""
 long_description = """
 AUIPC (add upper immediate topc) is used to buildpc-relative addresses and uses the U-typeformat.  AUIPC forms a 32-bit offset from the 20-bit U-immediate, filling in the lowest 12 bits withzeros, adds this offset to the address of the AUIPC instruction, then places the result in registerrd.
 """
 
 [ADD]
 name = "Add"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
 """

          
@@ 155,20 145,18 @@ ADD performs the addition of rs 1andrs2.
 
 [SUB]
 name = "SUB"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 ADD performs the addition of rs 1andrs2. SUB performs the subtraction of rs2 from rs1. Overflow sare ignored and the low XLEN bits of results are written to the destination rd.
 """
 
 [SLT]
 name = "Signed less than compare"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,
 SLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).

          
@@ 176,10 164,9 @@ SLTU rd,x0,rs2 sets rd to  1  if rs2 is 
 
 [SLTU]
 name = "Signed less than compare unsigned"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLT and SLTU perform signed and unsigned compares respectively, writing 1 tordifrs1<rs2, 0 otherwise.  Note,
 SLTU rd,x0,rs2 sets rd to  1  if rs2 is  not  equal  to  zero,  otherwise  sets rd to  zero  (assembler pseudoinstruction SNEZ rd, rs).

          
@@ 187,80 174,72 @@ SLTU rd,x0,rs2 sets rd to  1  if rs2 is 
 
 [AND]
 name = "AND"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 AND, OR, and XOR perform bitwise logical operations.
 """
 
 [OR]
 name = "OR"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 AND, OR, and XOR perform bitwise logical operations.
 """
 
 [XOR]
 name = "XOR"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 AND, OR, and XOR perform bitwise logical operations.
 """
 
 [SLL]
 name = "Shift left logical"
-opcode = ""
+opcode = "OP / "
 encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
 """
 
 [SRL]
 name = "Shift right logical"
-opcode = ""
-encoding = ""
+opcode = "OP / "
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
 """
 
 [SRA]
 name = "Shift right arithmetic"
-opcode = ""
-encoding = ""
+opcode = "OP / "
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value inregister rs1 by the shift amount held in the lower 5 bits of register rs2
 """
 
 [NOP]
 name = "No operation"
-opcode = ""
-encoding = "R"
+opcode = "OP-IMM / ADDI"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The NOP instruction does not change any architecturally visible state, except for advancing the pc and incrementing any applicable performance counters.  NOP is encoded as ADDI x0, x0, 0.
 """
 
 [J]
 name = "Unconditional jump"
-opcode = ""
+opcode = "JAL"
 encoding = "J"
 extension = "I"
-description = ""
 long_description = """
 Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
 a JAL with rd=x0.

          
@@ 268,20 247,18 @@ a JAL with rd=x0.
 
 [JAL]
 name = "Jump and link"
-opcode = ""
+opcode = "JAL"
 encoding = "J"
 extension = "I"
-description = ""
 long_description = """
 The  jump  and  link  (JAL)  instruction  uses  the  J-type  format,  where  the  J-immediate  encodes  asigned offset in multiples of 2 bytes.  The offset is sign-extended and added to the address of thejump instruction to form the jump target address.  Jumps can therefore target a±1 MiB range.  JAL stores the address of the instruction following the jump (pc+4) into register rd.  The standard software calling convention uses x1 as the return address register and x5 as an alternate link register
 """
 
 [JALR]
 name = "Jump and link register"
-opcode = ""
+opcode = "JAL"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
 address is obtained by adding the sign-extended 12-bit I-immediate to the register rs1, then setting

          
@@ 292,10 269,9 @@ required.
 
 [BEQ]
 name = "Branch if equal"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BEQ"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 308,10 284,9 @@ respectively
 
 [BNE]
 name = "Branch if not equal"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BNE"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 323,10 298,9 @@ respectively
 
 [BLT]
 name = "Branch if less than"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BLT"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 338,10 312,9 @@ respectively
 
 [BLTU]
 name = "Branch if less than unsigned"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BLTU"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 353,10 326,9 @@ respectively
 
 [BGE]
 name = "Branch if greater or equal"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BGE"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 368,10 340,9 @@ respectively
 
 [BGEU]
 name = "Branch if greater or equal unsigned"
-opcode = ""
-encoding = ""
+opcode = "BRANCH / BGEU"
+encoding = "B"
 extension = "I"
-description = ""
 long_description = """
 Branch instructions compare two registers. BEQ and BNE take the branch if registers rs1 and rs2
 are equal or unequal respectively. BLT and BLTU take the branch if rs1 is less than rs2, using

          
@@ 383,10 354,9 @@ respectively
 
 [LW]
 name = "Load word"
-opcode = ""
+opcode = "LOAD / width"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
 then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then

          
@@ 395,10 365,9 @@ zero extends to 32-bits before storing i
 
 [LH]
 name = "Load half word"
-opcode = ""
+opcode = "LOAD / width"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
 then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then

          
@@ 407,10 376,9 @@ zero extends to 32-bits before storing i
 
 [LHU]
 name = "Load half word unsigned"
-opcode = ""
+opcode = "LOAD / ???"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
 then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then

          
@@ 419,10 387,9 @@ zero extends to 32-bits before storing i
 
 [LB]
 name = "Load byte"
-opcode = ""
+opcode = "LOAD / width"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
 then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then

          
@@ 431,10 398,9 @@ zero extends to 32-bits before storing i
 
 [LBU]
 name = "Load byte unsigned"
-opcode = ""
+opcode = "LOAD / ???"
 encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The LW instruction loads a 32-bit value from memory into rd. LH loads a 16-bit value from memory,
 then sign-extends to 32-bits before storing in rd. LHU loads a 16-bit value from memory but then

          
@@ 444,10 410,9 @@ zero extends to 32-bits before storing i
 
 [SW]
 name = "Store word"
-opcode = ""
+opcode = "STORE / width"
 encoding = "S"
 extension = "I"
-description = ""
 long_description = """
 The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
 rs2 to memory

          
@@ 455,10 420,9 @@ rs2 to memory
 
 [SH]
 name = "Store half word"
-opcode = ""
+opcode = "STORE / width"
 encoding = "S"
 extension = "I"
-description = ""
 long_description = """
 The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
 rs2 to memory

          
@@ 466,10 430,9 @@ rs2 to memory
 
 [SB]
 name = "Store byte"
-opcode = ""
+opcode = "STORE / width"
 encoding = "S"
 extension = "I"
-description = ""
 long_description = """
 The SW, SH, and SB instructions store 32-bit, 16-bit, and 8-bit values from the low bits of register
 rs2 to memory

          
@@ 477,10 440,9 @@ rs2 to memory
 
 [FENCE]
 name = "Fence"
-opcode = ""
-encoding = ""
+opcode = "MISC-MEM / FENCE"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The FENCE instruction is used to order device I/O and memory accesses as
 viewed by other RISCV harts and external devices or coprocessors. Any

          
@@ 494,10 456,9 @@ provides a precise description of the RI
 
 [ECALL]
 name = "Environment call"
-opcode = ""
-encoding = ""
+opcode = "SYSTEM / PRIV / ECALL"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The ECALL instruction is used to make a service request to the execution environment. The EEI
 will define how parameters for the service request are passed, but usually these will be in defined

          
@@ 506,10 467,9 @@ locations in the integer register file
 
 [EBREAK]
 name = "Environment break point"
-opcode = ""
-encoding = ""
+opcode = "SYSTEM / PRIV / EBREAK"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 The EBREAK instruction is used to return control to a debugging environment.
 """

          
@@ 517,21 477,39 @@ The EBREAK instruction is used to return
 [HINT]
 name = "Hint"
 opcode = ""
-encoding = ""
+encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 RV32I reserves a large encoding space for HINT instructions, which are usually used to communicate performance hints to the microarchitecture. HINTs are encoded as integer computational
 instructions with rd=x0. Hence, like the NOP instruction, HINTs do not change any architecturally
 visible state, except for advancing the pc and any applicable performance counters. Implementations are always allowed to ignore the encoded hints.
 """
 
+[FENCE.I]
+name = "Fence"
+opcode = "MISC-MEM / FENCE.I"
+encoding = "I"
+extension = "Zifencei"
+long_description = """
+The FENCE.I instruction is used to synchronize the instruction and data streams. RISC-V does
+not guarantee that stores to instruction memory will be made visible to instruction fetches on a
+RISC-V hart until that hart executes a FENCE.I instruction. A FENCE.I instruction ensures that
+a subsequent instruction fetch on a RISC-V hart will see any previous data stores already visible to
+the same RISC-V hart. FENCE.I does not ensure that other RISC-V harts’ instruction fetches will
+observe the local hart’s stores in a multiprocessor system. To make a store to instruction memory
+visible to all RISC-V harts, the writing hart has to execute a data FENCE before requesting that
+all remote RISC-V harts execute a FENCE.I.
+
+The unused fields in the FENCE.I instruction, imm[11:0], rs1, and rd, are reserved for finer-grain
+fences in future extensions. For forward compatibility, base implementations shall ignore these
+fields, and standard software shall zero these fields.
+"""
+
 [ADDIW]
 name = "Add immediate word"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM-32 / ADDIW"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 ADDIW is an RV64I instruction that adds the sign-extended 12-bit immediate to register rs1
 and produces the proper sign-extension of a 32-bit result in rd. Overflows are ignored and the

          
@@ 542,10 520,9 @@ SEXT.W)
 
 [SLLIW]
 name = "Shift left logical immediate word"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM-32 / SLLIW"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with

          
@@ 554,10 531,9 @@ imm[5] ̸= 0 are reserved.
 
 [SRLIW]
 name = "Shift right logical immediate word"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM-32 / SLLIW"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with

          
@@ 567,10 543,9 @@ imm[5] ̸= 0 are reserved.
 
 [SRAIW]
 name = "Shift right arithmetic immediate word"
-opcode = ""
-encoding = ""
+opcode = "OP-IMM-32 / SRAIW"
+encoding = "I"
 extension = "I"
-description = ""
 long_description = """
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. SLLIW, SRLIW, and SRAIW encodings with

          
@@ 579,10 554,9 @@ imm[5] ̸= 0 are reserved.
 
 [ADDW]
 name = "Add word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / ADDW"
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
 but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low

          
@@ 591,10 565,9 @@ 32-bits of the result is sign-extended t
 
 [SUBW]
 name = "Subtract word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / SUBW"
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 ADDW and SUBW are RV64I-only instructions that are defined analogously to ADD and SUB
 but operate on 32-bit values and produce signed 32-bit results. Overflows are ignored, and the low

          
@@ 603,10 576,9 @@ 32-bits of the result is sign-extended t
 
 [SLLW]
 name = "Shift left logical word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / SLLW"
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]

          
@@ 614,10 586,9 @@ on 32-bit values and produce signed 32-b
 
 [SRLW]
 name = "Shift right logical word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / SRLW"
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]

          
@@ 625,10 596,9 @@ on 32-bit values and produce signed 32-b
 
 [SRAW]
 name = "Shift right arithmetic word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / SRAW"
+encoding = "R"
 extension = "I"
-description = ""
 long_description = """
 SLLW, SRLW, and SRAW are RV64I-only instructions that are analogously defined but operate
 on 32-bit values and produce signed 32-bit results. The shift amount is given by rs2[4:0]

          
@@ 639,7 609,6 @@ name = "Load absolute address"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Load absolute address, where delta = symbol − pc.
 

          
@@ 658,7 627,6 @@ name = "Load local address"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Load local address, where delta = symbol − pc
 

          
@@ 672,7 640,6 @@ name = "Load global byte/halfword/word/d
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Load global
 

          
@@ 685,7 652,6 @@ name = "Store global byte/halfword/word/
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Store global
 

          
@@ 698,7 664,6 @@ name = "Load immediate"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Load immediate.  Expands to "myriad sequences".
 """

          
@@ 708,7 673,6 @@ name = "Move"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Copy register
 

          
@@ 720,7 684,6 @@ name = "One's complement negate"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 One's complement negation.
 

          
@@ 732,7 695,6 @@ name = "Two's complement negate"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Two's complement negation.
 

          
@@ 744,7 706,6 @@ name = "Two's complement negate word"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Two's complement negation, word length.
 

          
@@ 757,7 718,6 @@ name = "Sign extend word"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 Sign extend word
 

          
@@ 769,7 729,6 @@ name = "Set if equal to zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 sltiu rd, rs, 1
 """

          
@@ 779,7 738,6 @@ name = "Set if not equal zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 sltu rd, x0, rs
 """

          
@@ 789,7 747,6 @@ name = "Set if less than zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 slt rd, rs, x0
 """

          
@@ 800,7 757,6 @@ name = "Set if greater than zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 lst rd, x0, rs
 """

          
@@ 810,7 766,6 @@ name = "Branch if equal to zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 beq rs, x0, offset
 """

          
@@ 820,7 775,6 @@ name = "Branch if not equal zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bne rs, x0, offset
 """

          
@@ 830,7 784,6 @@ name = "Branch if less than zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bge x0, rs, offset
 """

          
@@ 841,7 794,6 @@ name = "Branch if greater or equal to ze
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bge rs, x0, offset
 """

          
@@ 851,7 803,6 @@ name = "Branch if less than zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 blt rs, x0, offset
 """

          
@@ 861,7 812,6 @@ name = "Branch if greater than zero"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 blt x0, rs, offset
 """

          
@@ 871,7 821,6 @@ name = "Branch if greater than"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 blt rt, rs, offset
 """

          
@@ 882,7 831,6 @@ name = "Branch if less than or equal"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bge rt, rs, offset
 """

          
@@ 892,7 840,6 @@ name = "Branch if greater than, unsigned
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bltu rt, rs, offset
 """

          
@@ 902,7 849,6 @@ name = "Branch if less than, unsigned"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 bgeu rt, rs, offset
 """

          
@@ 912,7 858,6 @@ name = "Jump register"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 jalr x0, 0(rs)
 """

          
@@ 923,7 868,6 @@ name = "Return from subroutine"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 jalr x0, 0(x1)
 """

          
@@ 933,7 877,6 @@ name = "Call far-away subroutine"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 auipc x1, offset[31 : 12] + offset[11]
 jalr x1, offset[11:0](x1)

          
@@ 944,7 887,6 @@ name = "Tail call far-away subroutine"
 opcode = ""
 encoding = "pseudo"
 extension = "I"
-description = ""
 long_description = """
 auipc x6, offset[31 : 12] + offset[11]
 jalr x0, offset[11:0](x6)

          
@@ 952,10 894,9 @@ jalr x0, offset[11:0](x6)
 
 [MUL]
 name = "Multiply"
-opcode = ""
-encoding = ""
+opcode = "OP / MUL / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
 in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-

          
@@ 970,10 911,9 @@ two separate multiplies.
 
 [MULH]
 name = "Multiply high"
-opcode = ""
-encoding = ""
-extension = ""
-description = ""
+opcode = "OP / MULH / MULDIV"
+encoding = "R"
+extension = "M"
 long_description = """
 MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
 in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-

          
@@ 988,10 928,9 @@ two separate multiplies.
 
 [MULHU]
 name = "Multiply high unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP / MULHW / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
 in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-

          
@@ 1006,10 945,9 @@ two separate multiplies.
 
 [MULHSU]
 name = "Multiply high signed-unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP / MULHSW / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
 in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-

          
@@ 1024,10 962,9 @@ two separate multiplies.
 
 [MULW]
 name = "Multiply word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / MULW / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the
 sign-extension of the lower 32 bits of the result into the destination register.

          
@@ 1036,10 973,9 @@ sign-extension of the lower 32 bits of t
 
 [DIV]
 name = "Divide"
-opcode = ""
-encoding = ""
+opcode = "OP / DIV / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
 rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division

          
@@ 1053,10 989,9 @@ separate divides.
 
 [DIVU]
 name = "Divide unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP / DIVU / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
 rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division

          
@@ 1070,10 1005,9 @@ separate divides.
 
 [REM]
 name = "Remainder"
-opcode = ""
-encoding = ""
+opcode = "OP / REM / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
 rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division

          
@@ 1087,10 1021,9 @@ separate divides.
 
 [REMU]
 name = "Remainder unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP / REMU / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
 rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division

          
@@ 1104,10 1037,9 @@ separate divides.
 
 [DIVW]
 name = "Divide word"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / DIVW / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
 long_description = """
 DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient

          
@@ 1118,10 1050,35 @@ always sign-extend the 32-bit result to 
 
 [DIVUW]
 name = "Divide word unsigned"
-opcode = ""
-encoding = ""
+opcode = "OP-32 / DIVUW / MULDIV"
+encoding = "R"
 extension = "M"
-description = ""
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[REMW]
+name = "Remainder word"
+opcode = "OP-32 / REMW / MULDIV"
+encoding = "R"
+extension = "M"
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[REMUW]
+name = "Remainder word unsigned"
+opcode = "OP-32 / REMUW / MULDIV"
+encoding = "R"
+extension = "M"
 long_description = """
 DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
 bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient

          
@@ 1135,7 1092,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1144,7 1100,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1154,7 1109,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1163,7 1117,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1172,7 1125,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1181,7 1133,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1190,7 1141,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1199,7 1149,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1208,7 1157,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1217,7 1165,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1226,7 1173,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1235,7 1181,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1244,7 1189,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1253,7 1197,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1262,7 1205,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1271,7 1213,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1280,7 1221,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """
 

          
@@ 1289,7 1229,6 @@ name = ""
 opcode = ""
 encoding = ""
 extension = ""
-description = ""
 long_description = """
 """