31cd84262750 — Simon Heath 1 year, 5 months ago 
Add M extension and clarify extension versions
patch browse 
2 files changed, 352 insertions(+), 18 deletions(-)

M README.md
M instructions.toml

M README.md +18 -18
@@ 40,35 40,35 @@ is the latest formally published one, da
 probably be a new one along soon.  Another file for the privileged
 instruction set would be nice but I'm not gonna go there myself yet.
 
-RV32 is currently out of scope.
+RV32 is currently out of scope, but might be nice in the future.
 
 Possible states:
 
  * Finished -- Finished
- * Rough -- All instructions listed but not all complete and proofread
- * WIP -- Not all instructions listed
+ * Rough -- All instructions listed and complete, but not proofread or
+   cleaned up
+ * WIP -- Not all instructions listed, or instructions listed but
+   missing info
  * Not started -- Not started
 
 Extension and state:
 
- * **I:** Rough
- * **M:** Not started
- * **A:** Not started
- * **Zicsr:** Not started
- * **Counters:** Not started
- * **F:** Not started
- * **D:** Not started
- * **Q:** Not started
- * **RVWMO:** Not started
- * **L:** Not started
- * **C:** Not started
- * **B:** Not started
- * **J:** Not started
- * **T:** Not started
- * **P:** Not started
+ * **I:** WIP, version 2.1
+ * **M:** WIP, version 2.0
+ * **A:** Not started, version 2.1
+ * **Zfencei:** Not started, version 2.0
+ * **Zicsr:** Not started, version 2.0
+ * **F:** Not started, version 2.2
+ * **D:** Not started, version 2.2
+ * **Q:** Not started, version 2.2
+ * **C:** Not started, version 2.0
+
+Extensions to do later:
+
  * **V:** Not started
  * **Zam:** Not started
  * **Ztso:** Not started
+ * Probably others
 
 # Things to ponder
 

          
M instructions.toml +334 -0
@@ 950,6 950,195 @@ auipc x6, offset[31 : 12] + offset[11]
 jalr x0, offset[11:0](x6)
 """
 
+[MUL]
+name = "Multiply"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULH]
+name = "Multiply high"
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULHU]
+name = "Multiply high unsigned"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULHSU]
+name = "Multiply high signed-unsigned"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+MUL performs an XLEN-bit×XLEN-bit multiplication of rs1 by rs2 and places the lower XLEN bits
+in the destination register. MULH, MULHU, and MULHSU perform the same multiplication but re-
+turn the upper XLEN bits of the full 2×XLEN-bit product, for signed×signed, unsigned×unsigned,
+and signed rs1×unsigned rs2 multiplication, respectively. If both the high and low bits of the same
+product are required, then the recommended code sequence is: MULH[[S]U] rdh, rs1, rs2; MUL
+rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be the same as rs1 or
+rs2). Microarchitectures can then fuse these into a single multiply operation instead of performing
+two separate multiplies.
+"""
+
+
+[MULW]
+name = "Multiply word"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+MULW is an RV64 instruction that multiplies the lower 32 bits of the source registers, placing the
+sign-extension of the lower 32 bits of the result into the destination register.
+"""
+
+
+[DIV]
+name = "Divide"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[DIVU]
+name = "Divide unsigned"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[REM]
+name = "Remainder"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[REMU]
+name = "Remainder unsigned"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIV and DIVU perform an XLEN bits by XLEN bits signed and unsigned integer division of rs1 by
+rs2, rounding towards zero. REM and REMU provide the remainder of the corresponding division
+operation. For REM, the sign of the result equals the sign of the dividend.
+For both signed and unsigned division, it holds that dividend = divisor × quotient + remainder.
+If both the quotient and remainder are required from the same division, the recommended code
+sequence is: DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2 (rdq cannot be the same as rs1 or rs2).
+Microarchitectures can then fuse these into a single divide operation instead of performing two
+separate divides.
+"""
+
+[DIVW]
+name = "Divide word"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[DIVUW]
+name = "Divide word unsigned"
+opcode = ""
+encoding = ""
+extension = "M"
+description = ""
+long_description = """
+DIVW and DIVUW are RV64 instructions that divide the lower 32 bits of rs1 by the lower 32
+bits of rs2, treating them as signed and unsigned integers respectively, placing the 32-bit quotient
+in rd, sign-extended to 64 bits. REMW and REMUW are RV64 instructions that provide the
+corresponding signed and unsigned remainder operations respectively. Both REMW and REMUW
+always sign-extend the 32-bit result to 64 bits, including on a divide by zero.
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
 []
 name = ""
 opcode = ""

          
@@ 960,3 1149,148 @@ long_description = """
 """
 
 
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+[]
+name = ""
+opcode = ""
+encoding = ""
+extension = ""
+description = ""
+long_description = """
+"""
+
+