~icefox/riscv-reference commit

2 files changed, 15 insertions(+), 15 deletions(-)

M README.md
M instructions.toml

M README.md +3 -3

@@ 43,7 43,7 @@ instruction set would be nice but I'm no
 RV32 is currently out of scope, but might be nice in the future.
 Apparently some instruction encodings are different between RV32 and
 RV64, such as SLLI, SRLI, and SRAI, so I'm not going to bother worrying
-about both.
+about both for now.
 
 Possible states:
 

          
@@ 63,8 63,8 @@ Extension and state:
  * **D:** Not started, version 2.2
  * **Q:** Not started, version 2.2
  * **C:** Not started, version 2.0
- * **Zicsr:** WIP, version 2.0
- * **Zifencei:** Not started, version 2.0
+ * **Zicsr:** Not started, version 2.0
+ * **Zifencei:** WIP, version 2.0
 
 Extensions to do later:

M instructions.toml +12 -12

@@ 135,7 135,7 @@ AUIPC (add upper immediate topc) is used
 
 [ADD]
 name = "Add"
-opcode = "OP / "
+opcode = "OP / ADD / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 145,7 145,7 @@ ADD performs the addition of rs 1andrs2.
 
 [SUB]
 name = "SUB"
-opcode = "OP / "
+opcode = "OP / SUB / 0b0100000"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 154,7 154,7 @@ ADD performs the addition of rs 1andrs2.
 
 [SLT]
 name = "Signed less than compare"
-opcode = "OP / "
+opcode = "OP / SLT / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 164,7 164,7 @@ SLTU rd,x0,rs2 sets rd to  1  if rs2 is 
 
 [SLTU]
 name = "Signed less than compare unsigned"
-opcode = "OP / "
+opcode = "OP / SLTU / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 174,7 174,7 @@ SLTU rd,x0,rs2 sets rd to  1  if rs2 is 
 
 [AND]
 name = "AND"
-opcode = "OP / "
+opcode = "OP / AND / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 183,7 183,7 @@ AND, OR, and XOR perform bitwise logical
 
 [OR]
 name = "OR"
-opcode = "OP / "
+opcode = "OP / OR / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 192,7 192,7 @@ AND, OR, and XOR perform bitwise logical
 
 [XOR]
 name = "XOR"
-opcode = "OP / "
+opcode = "OP / XOR / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 201,7 201,7 @@ AND, OR, and XOR perform bitwise logical
 
 [SLL]
 name = "Shift left logical"
-opcode = "OP / "
+opcode = "OP / SLL / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 210,7 210,7 @@ SLL, SRL, and SRA perform logical left, 
 
 [SRL]
 name = "Shift right logical"
-opcode = "OP / "
+opcode = "OP / SRL / 0"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 219,7 219,7 @@ SLL, SRL, and SRA perform logical left, 
 
 [SRA]
 name = "Shift right arithmetic"
-opcode = "OP / "
+opcode = "OP / SRA / 0b0100000"
 encoding = "R"
 extension = "I"
 long_description = """

          
@@ 376,7 376,7 @@ zero extends to 32-bits before storing i
 
 [LHU]
 name = "Load half word unsigned"
-opcode = "LOAD / ???"
+opcode = "LOAD / width"
 encoding = "I"
 extension = "I"
 long_description = """

          
@@ 398,7 398,7 @@ zero extends to 32-bits before storing i
 
 [LBU]
 name = "Load byte unsigned"
-opcode = "LOAD / ???"
+opcode = "LOAD / width"
 encoding = "I"
 extension = "I"
 long_description = """