articles / sources: Use spaces instead of tabs in preformatted blocks.

Since tabs don’t show well on mobile, 4-space indentation is more compact.
M articles/keymatrix.php +13 -14
@@ 157,11 157,11 @@ 
 </table>
 
 <pre>
-	in	a,(#AA)
-	and	#F0		;only change bits 0-3
-	or	b		;take row number from B
-	out	(#AA),a
-	in	a,(#A9)		;read row into A
+    in a,(#AA)
+    and #F0         ; only change bits 0-3
+    or b            ; take row number from B
+    out (#AA),a
+    in a,(#A9)      ; read row into A
 </pre>
 
 

          
@@ 170,20 170,19 @@ 
 <p>In the following example I will show you how to read out the space key its status. The space key is located in bit 0 of row 8:</p>
 
 <pre>
-keys:	EQU	#FBE5
-
+keys: EQU #FBE5
 
-Main_ReadKeys:
 ;
-;Check whether space is pressed
+; Check whether space is pressed
 ;
-	ld	a,(keys+8)	;space
-	bit	0,a
-	jp	z,spacepressed
+Main_ReadKeys:
+    ld a,(keys+8)   ; space
+    bit 0,a
+    jp z,spacepressed
 
-	...
+    ...
 
-	ret
+    ret
 </pre>
 
 <p>The key readout itself is pretty trivial, however as you can see, I have put the key readout routines in a subroutine. It is good practice to do this because then the key handlers will in effect be called as subroutines so they can quite with a RET instead of having to manually JP back to the mainloop afterwards... <a href="http://www.acm.org/classics/oct95/">Go To Statement Considered Harmful</a>, eh ;). Actually the real objection against it in this case is that it introduces redundant code (being the “JP main” at the end of each keyhandler), which is bad; if you change something like for example the spot of the main routine which has to be jumped to, all those keyhandler exit jumps need to be changed and it is easy to forget one.</p>

          
M articles/mult_div_shifts.php +207 -201
@@ 41,18 41,18 @@ 
 <p>When you shift a register 1 bit to the left, you multiply the value of the register with 2. This shifting can be done using the SLA r instruction. By doing several shifts in sequence you can very easily multiply by any power of 2. For example:</p>
 
 <pre>
-	ld b,3		;Multiply 3 with 4
-	sla b		;x4
-	sla b		;result: b = 12
+    ld b,3          ; Multiply 3 with 4
+    sla b           ; x4
+    sla b           ; result: b = 12
 </pre>
 
 <p>If you use register A you can multiply faster by using the ADD A,A instruction, which is 5 T-states per instruction instead of 8. So ADD A,A is exactly the same as SLA A, or a multiplication by two. On a sidenote, instead of using ADD A,A, you can also use RLCA, which effectively behaves the same.</p>
 
 <pre>
-	ld a,15		;Multiply 15 with 8
-	add a,a		;x8
-	add a,a
-	add a,a		;result: a = 120
+    ld a,15         ; Multiply 15 with 8
+    add a,a         ; x8
+    add a,a
+    add a,a         ; result: a = 120
 </pre>
 
 <p>When programming multiplications you must always make sure the result will never exeed 255, in other words a carry may not occur. In the case of that happening, RLCA actually acts different from SLA A or ADD A,A (in some cases more usable, in some cases less usable). But generally that isn’t of any concern because when register A overflows the result will generally not be of much use anymore.</p>

          
@@ 60,13 60,13 @@ 
 <p>If you want to multiply by another value than a power of two, you can almost always achieve the desired result by storing inbetween values during the shifting and adding or subtracting them up afterwards. A few examples:</p>
 
 <pre>
-	ld a,5		;Multiply 5 with 20 (= A x 16 + A x 4)
-	add a,a		;x16
-	add a,a
-	ld b,a		;Store value of A x 4 in B
-	add a,a
-	add a,a
-	add a,b		;Add A x 4 to A x 16, result: a = 100
+    ld a,5          ; Multiply 5 with 20 (= A x 16 + A x 4)
+    add a,a         ; x16
+    add a,a
+    ld b,a          ; Store value of A x 4 in B
+    add a,a
+    add a,a
+    add a,b         ; Add A x 4 to A x 16, result: a = 100
 </pre>
 
 <p>If you would want to multiply with 22, you would also save the value after the first add in a register and add it to the total afterwards.</p>

          
@@ 74,13 74,13 @@ 
 <p>Sometimes, you can also use substractions to achieve your goals faster. For example, the multiplication of A with 15. This can be done by using the method described above, however, in that case you’ll need 4 temporary registers, and four additional adds afterwards. This could better be done as follows, which requires 1 more multiplication but only uses 1 temporary register and 1 subtraction afterwards:</p>
 
 <pre>
-	ld a,3		;Multiply 3 with 15 (= A x 16 - A x 1)
-	ld b,a		;Store value of A x 1 in B
-	add a,a		;x16
-	add a,a
-	add a,a
-	add a,a
-	sub b		;result: a = 45
+    ld a,3          ; Multiply 3 with 15 (= A x 16 - A x 1)
+    ld b,a          ; Store value of A x 1 in B
+    add a,a         ; x16
+    add a,a
+    add a,a
+    add a,a
+    sub b           ; result: a = 45
 </pre>
 
 

          
@@ 89,19 89,19 @@ 
 <p>Now, divisions are very much like multiplications. If a multiplication routine is complex, a division routine is even more so. However, using shifts it’s all too easy to divide in Assembly. It is done by simply shifting the other way, to the right. For this, you should use the SRL r instruction. An example:</p>
 
 <pre>
-	ld b,3		;Divide 18 by 4
-	srl b		;x4
-	srl b		;result: b = 4 (rest 2 is lost)
+    ld b,3          ; Divide 18 by 4
+    srl b           ; x4
+    srl b           ; result: b = 4 (rest 2 is lost)
 </pre>
 
 <p>There is no real fast alternative to a shift right when using register A. As an alternative, you can use RRCA for that. However, when using RRCA you must make sure there will be no rest, otherwise the result won’t be correct. This can be achieved by ANDing the original value with a value clearing the lower bits (which would otherwise be rotated out), or by making sure you are using values which are always a multiple of the divider.</p>
 
 <pre>
-	ld a,153	;Divide 153 by 8
-	and a,%11111000	;Clear bits 0-2 (equals 256 - 8)
-	rrca		;/8
-	rrca
-	rrca		;result: a = 19
+    ld a,153        ; Divide 153 by 8
+    and a,%11111000 ; Clear bits 0-2 (equals 256 - 8)
+    rrca            ; /8
+    rrca
+    rrca            ; result: a = 19
 </pre>
 
 <p>Dividing with values other than powers of 2 is trickier and is often not possible. If you want to see for yourself, try to construct a routine which divides 100 by 20. To know if a value can be divided, you must look at the amount of trailing zeroes in the binary representation of that value. The maximum number of RRCA’s you can use is then equal to that number. If you look at the beforementioned value 100 in binary (%01100100), you will see there are two trailing zeroes. Therefor, the division routine can only use 2 RRCA’s, while dividing by 20 needs 4 of them.</p>

          
@@ 114,21 114,21 @@ 
 <p>There are also ways to shift 16-bit registers. This is done using a 8-bit shift in combination with an 8-bit rotate and the carry bit. To shift a register DE one bit to the left you should use:</p>
 
 <pre>
-	sla e
-	rl d
+    sla e
+    rl d
 </pre>
 
 <p>To shift it one bit to the right (now with BC as example), use:</p>
 
 <pre>
-	srl b
-	rr c
+    srl b
+    rr c
 </pre>
 
 <p>Unfortunately, generally those 16-bit shifts are rather slow compared to 8-bit shifts (which will most often take place in the fast A register, which makes them almost 4 times as fast). However, just as with the 8-bit shifts, there is also the possibility to do faster 16-bit shifts to the left using the ADD instruction.</p>
 
 <pre>
-	add hl,hl	;shift HL 1 bit left... hl = hl x 2
+    add hl,hl       ; shift HL 1 bit left... hl = hl x 2
 </pre>
 
 <p>So, the best way to multiply 16-bit values is by using register HL in combination with ADD HL,HL instructions.</p>

          
@@ 155,84 155,87 @@ 
 
 <pre>
 ;
-;Multiply 8-bit values
-;In:  Multiply H with E
-;Out: HL = result
+; Multiply 8-bit values
+; In:  Multiply H with E
+; Out: HL = result
 ;
 Mult8:
-	ld d,0
-	ld l,d
-	ld b,8
+    ld d,0
+    ld l,d
+    ld b,8
 Mult8_Loop:
-	add hl,hl
-	jr nc,Mult8_NoAdd
-	add hl,de
+    add hl,hl
+    jr nc,Mult8_NoAdd
+    add hl,de
 Mult8_NoAdd:
-	djnz Mult8_Loop
-	ret
+    djnz Mult8_Loop
+    ret
 </pre>
 
 <pre>
 ;
-;Multiply 8-bit value with a 16-bit value
-;In: Multiply A with DE
-;Out: HL = result
+; Multiply 8-bit value with a 16-bit value
+; In: Multiply A with DE
+; Out: HL = result
 ;
-Mult12:	ld l,0
-	ld b,8
+Mult12:
+    ld l,0
+    ld b,8
 Mult12_Loop:
-	add hl,hl
-	add a,a
-	jr nc,Mult12_NoAdd
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12_NoAdd
+    add hl,de
 Mult12_NoAdd:
-	djnz Mult12_Loop
-	ret
+    djnz Mult12_Loop
+    ret
 </pre>
 
 <pre>
 ;
-;Multiply 16-bit values (with 16-bit result)
-;In: Multiply BC with DE
-;Out: HL = result
+; Multiply 16-bit values (with 16-bit result)
+; In: Multiply BC with DE
+; Out: HL = result
 ;
-Mult16:	ld a,b
-	ld b,16
+Mult16:
+    ld a,b
+    ld b,16
 Mult16_Loop:
-	add hl,hl
-	sla c
-	rla
-	jr nc,Mult16_NoAdd
-	add hl,de
+    add hl,hl
+    sla c
+    rla
+    jr nc,Mult16_NoAdd
+    add hl,de
 Mult16_NoAdd:
-	djnz Mult16_Loop
-	ret
+    djnz Mult16_Loop
+    ret
 </pre>
 
 <pre>
 ;
-;Multiply 16-bit values (with 32-bit result)
-;In: Multiply BC with DE
-;Out: BCHL = result
+; Multiply 16-bit values (with 32-bit result)
+; In: Multiply BC with DE
+; Out: BCHL = result
 ;
-Mult32:	ld a,c
-	ld c,b
-	ld hl,0
-	ld b,16
+Mult32:
+    ld a,c
+    ld c,b
+    ld hl,0
+    ld b,16
 Mult32_Loop:
-	add hl,hl
-	rla
-	rl c
-	jr nc,Mult32_NoAdd
-	add hl,de
-	adc a,0
-	jp nc,Mult32_NoAdd
-	inc c
+    add hl,hl
+    rla
+    rl c
+    jr nc,Mult32_NoAdd
+    add hl,de
+    adc a,0
+    jp nc,Mult32_NoAdd
+    inc c
 Mult32_NoAdd:
-	djnz Mult32_Loop
-	ld b,c
-	ld c,a
-	ret
+    djnz Mult32_Loop
+    ld b,c
+    ld c,a
+    ret
 </pre>
 
 <h3 id="rrmultr">Right-rotating multiplication</h3>

          
@@ 277,23 280,23 @@ 8-bit: 509 T-states<br />
 
 <pre>
 ;
-;Multiply 8-bit value with a 16-bit value (right rotating)
-;In: Multiply A with DE
-;     Put lowest value in A for most efficient calculation
-;Out: HL = result
+; Multiply 8-bit value with a 16-bit value (right rotating)
+; In: Multiply A with DE
+;      Put lowest value in A for most efficient calculation
+; Out: HL = result
 ;
 Mult12R:
-	ld hl,0
+    ld hl,0
 Mult12R_Loop:
-	srl a
-	jr nc,Mult12R_NoAdd
-	add hl,de
+    srl a
+    jr nc,Mult12R_NoAdd
+    add hl,de
 Mult12R_NoAdd:
-	sla e
-	rl d
-	or a
-	jp nz,Mult12R_Loop
-	ret
+    sla e
+    rl d
+    or a
+    jp nz,Mult12R_Loop
+    ret
 </pre>
 
 <h3 id="ulrmultr">Unrolled left-rotating multiplication</h3>

          
@@ 304,51 307,51 @@ Mult12R_NoAdd:
 
 <pre>
 ;
-;Multiply 8-bit value with a 16-bit value (unrolled)
-;In: Multiply A with DE
-;Out: HL = result
+; Multiply 8-bit value with a 16-bit value (unrolled)
+; In: Multiply A with DE
+; Out: HL = result
 ;
 Mult12U:
-	ld l,0
-	add a,a
-	jr nc,Mult12U_NoAdd0
-	add hl,de
+    ld l,0
+    add a,a
+    jr nc,Mult12U_NoAdd0
+    add hl,de
 Mult12U_NoAdd0:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd1
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd1
+    add hl,de
 Mult12U_NoAdd1:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd2
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd2
+    add hl,de
 Mult12U_NoAdd2:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd3
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd3
+    add hl,de
 Mult12U_NoAdd3:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd4
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd4
+    add hl,de
 Mult12U_NoAdd4:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd5
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd5
+    add hl,de
 Mult12U_NoAdd5:
-	add hl,hl
-	add a,a
-	jr nc,Mult12U_NoAdd6
-	add hl,de
+    add hl,hl
+    add a,a
+    jr nc,Mult12U_NoAdd6
+    add hl,de
 Mult12U_NoAdd6:
-	add hl,hl
-	add a,a
-	ret nc
-	add hl,de
-	ret
+    add hl,hl
+    add a,a
+    ret nc
+    add hl,de
+    ret
 </pre>
 
 <p>It is also worthwhile to unroll the other multiplication routines. For the Mult8 routine for example, it saves 115 out of 367 T-states on average, that’s 31% faster, at the cost of just 38 bytes (14 → 52).</p>

          
@@ 375,63 378,65 @@ Output: #528 (#5.28 or 5,15625 decimal)<
 
 <pre>
 ;
-;Divide 8-bit values
-;In: Divide E by divider C
-;Out: A = result, B = rest
+; Divide 8-bit values
+; In: Divide E by divider C
+; Out: A = result, B = rest
 ;
-Div8:	xor a
-	ld b,8
+Div8:
+    xor a
+    ld b,8
 Div8_Loop:
-	rl e
-	rla
-	sub c
-	jr nc,Div8_NoAdd
-	add a,c
+    rl e
+    rla
+    sub c
+    jr nc,Div8_NoAdd
+    add a,c
 Div8_NoAdd:
-	djnz Div8_Loop
-	ld b,a
-	ld a,e
-	rla
-	cpl
-	ret
+    djnz Div8_Loop
+    ld b,a
+    ld a,e
+    rla
+    cpl
+    ret
 </pre>
 
 <pre>
 ;
-;Divide 16-bit values (with 16-bit result)
-;In: Divide BC by divider DE
-;Out: BC = result, HL = rest
+; Divide 16-bit values (with 16-bit result)
+; In: Divide BC by divider DE
+; Out: BC = result, HL = rest
 ;
-Div16:	ld hl,0
-	ld a,b
-	ld b,8
+Div16:
+    ld hl,0
+    ld a,b
+    ld b,8
 Div16_Loop1:
-	rla
-	adc hl,hl
-	sbc hl,de
-	jr nc,Div16_NoAdd1
-	add hl,de
+    rla
+    adc hl,hl
+    sbc hl,de
+    jr nc,Div16_NoAdd1
+    add hl,de
 Div16_NoAdd1:
-	djnz Div16_Loop1
-	rla
-	cpl
-	ld b,a
-	ld a,c
-	ld c,b
-	ld b,8
+    djnz Div16_Loop1
+    rla
+    cpl
+    ld b,a
+    ld a,c
+    ld c,b
+    ld b,8
 Div16_Loop2:
-	rla
-	adc hl,hl
-	sbc hl,de
-	jr nc,Div16_NoAdd2
-	add hl,de
+    rla
+    adc hl,hl
+    sbc hl,de
+    jr nc,Div16_NoAdd2
+    add hl,de
 Div16_NoAdd2:
-	djnz Div16_Loop2
-	rla
-	cpl
-	ld b,c
-	ld c,a
-	ret
+    djnz Div16_Loop2
+    rla
+    cpl
+    ld b,c
+    ld c,a
+    ret
 </pre>
 
 <p><i>Thanks to Flyguille for the Div16 routine, taken from his MNBIOS source code.</i></p>

          
@@ 481,29 486,30 @@ DIV9:   INC     HL              ;  7    
 
 <pre>
 ;
-;Square root of 16-bit value
-;In:  HL = value
-;Out:  D = result (rounded down)
+; Square root of 16-bit value
+; In:  HL = value
+; Out:  D = result (rounded down)
 ;
-Sqr16:	ld de,#0040
-	ld a,l
-	ld l,h
-	ld h,d
-	or a
-	ld b,8
+Sqr16:
+    ld de,#0040
+    ld a,l
+    ld l,h
+    ld h,d
+    or a
+    ld b,8
 Sqr16_Loop:
-	sbc hl,de
-	jr nc,Sqr16_Skip
-	add hl,de
+    sbc hl,de
+    jr nc,Sqr16_Skip
+    add hl,de
 Sqr16_Skip:
-	ccf
-	rl d
-	add a,a
-	adc hl,hl
-	add a,a
-	adc hl,hl
-	djnz Sqr16_Loop
-	ret
+    ccf
+    rl d
+    add a,a
+    adc hl,hl
+    add a,a
+    adc hl,hl
+    djnz Sqr16_Loop
+    ret
 </pre>
 
 

          
M articles/psg_sample.php +86 -86
@@ 72,7 72,7 @@ 
     <msup>
       <mn>2</mn>
       <mrow>
-	  	<mo>-</mo>
+        <mo>-</mo>
         <mfenced>
           <mrow>
             <mfrac>

          
@@ 200,99 200,99 @@ 
 <p>I created a C# program to calculate what combinations of volumes would have to be used, and to brute force check over what range the deviations would be the least. Without boring you with all the specific details, I have found that when running over a range from 0 to 1.328 (out of 3), the signal-to-noise ratio is the best. The resulting lookup table for that range, mapping 8-bit sample values to PSG channel volumes, is included in the replay routine below:</p>
 
 <pre>;
-;PSG sample replay routine
+; PSG sample replay routine
 ;
-;hl = sample start address
-;de = sample length
+; hl = sample start address
+; de = sample length
 ;
-	exx
-	ld c,#A1
-	ld d,0
-	exx
+    exx
+    ld c,#A1
+    ld d,0
+    exx
 Loop:
-	ld a,(hl)
-	inc hl
-	exx
-	ld e,a
-	ld hl,PSG_SAMPLE_TABLE
-	add hl,de
-	ld b,(hl)
-	inc h
-	ld e,(hl)
-	inc h
-	ld h,(hl)
-	ld a,8
-	out (#A0),a		;play as fast as possible
-	inc a
-	out (c),b
-	out (#A0),a
-	out (c),e
-	inc a
-	out (#A0),a
-	out (c),h
-	
-	ld b,8			;timing wait loop
+    ld a,(hl)
+    inc hl
+    exx
+    ld e,a
+    ld hl,PSG_SAMPLE_TABLE
+    add hl,de
+    ld b,(hl)
+    inc h
+    ld e,(hl)
+    inc h
+    ld h,(hl)
+    ld a,8
+    out (#A0),a     ; play as fast as possible
+    inc a
+    out (c),b
+    out (#A0),a
+    out (c),e
+    inc a
+    out (#A0),a
+    out (c),h
+    
+    ld b,8          ; timing wait loop
 WaitLoop:
-	djnz WaitLoop
+    djnz WaitLoop
 
-	exx
-	dec de
-	ld a,d
-	or e
-	jp nz,Loop
-	ret
-	
+    exx
+    dec de
+    ld a,d
+    or e
+    jp nz,Loop
+    ret
+
 PSG_SAMPLE_TABLE:
-	DB  00,01,02,03,04,03,05,03,04,05,06,06,05,06,06,06
-	DB  06,06,07,06,07,08,08,08,07,07,09,07,09,09,08,08
-	DB  09,09,08,09,09,09,09,09,10,10,10,10,09,09,10,10
-	DB  10,10,09,10,11,11,11,11,11,11,11,11,10,10,10,11
-	DB  11,11,11,11,11,11,11,12,11,11,12,12,11,12,11,12
-	DB  12,12,12,11,12,11,12,12,12,12,11,12,12,12,12,11
-	DB  12,13,12,13,11,13,13,13,13,13,13,11,13,13,13,13
-	DB  13,13,13,12,13,13,13,12,12,13,12,13,13,13,13,13
-	DB  13,12,13,13,13,13,13,13,13,14,13,13,14,14,14,14
-	DB  14,14,13,14,14,13,14,14,14,14,14,14,13,14,14,14
-	DB  14,14,14,13,14,14,13,14,14,13,13,14,14,14,14,14
-	DB  14,14,14,14,13,14,14,13,14,14,14,14,14,14,13,14
-	DB  14,14,15,14,15,15,15,15,15,15,15,15,15,15,15,15
-	DB  14,15,15,15,15,15,15,14,15,15,15,15,15,15,15,15
-	DB  15,15,15,15,15,15,15,15,15,15,15,14,15,14,14,14
-	DB  14,14,15,15,14,15,15,14,15,15,15,15,15,15,15,14
+    db 00,01,02,03,04,03,05,03,04,05,06,06,05,06,06,06
+    db 06,06,07,06,07,08,08,08,07,07,09,07,09,09,08,08
+    db 09,09,08,09,09,09,09,09,10,10,10,10,09,09,10,10
+    db 10,10,09,10,11,11,11,11,11,11,11,11,10,10,10,11
+    db 11,11,11,11,11,11,11,12,11,11,12,12,11,12,11,12
+    db 12,12,12,11,12,11,12,12,12,12,11,12,12,12,12,11
+    db 12,13,12,13,11,13,13,13,13,13,13,11,13,13,13,13
+    db 13,13,13,12,13,13,13,12,12,13,12,13,13,13,13,13
+    db 13,12,13,13,13,13,13,13,13,14,13,13,14,14,14,14
+    db 14,14,13,14,14,13,14,14,14,14,14,14,13,14,14,14
+    db 14,14,14,13,14,14,13,14,14,13,13,14,14,14,14,14
+    db 14,14,14,14,13,14,14,13,14,14,14,14,14,14,13,14
+    db 14,14,15,14,15,15,15,15,15,15,15,15,15,15,15,15
+    db 14,15,15,15,15,15,15,14,15,15,15,15,15,15,15,15
+    db 15,15,15,15,15,15,15,15,15,15,15,14,15,14,14,14
+    db 14,14,15,15,14,15,15,14,15,15,15,15,15,15,15,14
 
-	DB  00,00,00,00,00,02,00,02,02,03,01,02,04,04,03,04
-	DB  04,05,04,05,05,02,03,04,06,06,01,06,02,03,06,07
-	DB  05,06,07,06,06,06,07,06,04,04,05,06,08,07,06,06
-	DB  07,06,08,07,03,04,03,04,04,05,05,05,08,09,09,07
-	DB  07,07,08,07,08,08,08,02,08,09,03,05,09,05,08,06
-	DB  06,07,06,10,07,09,08,07,08,08,09,08,08,09,08,10
-	DB  09,00,08,01,10,02,03,04,04,05,06,10,06,06,06,07
-	DB  06,07,07,10,08,08,07,11,11,08,11,08,09,09,09,08
-	DB  09,11,09,09,10,10,10,10,10,00,10,09,02,02,04,03
-	DB  04,04,11,05,05,11,07,07,07,07,07,08,10,08,08,08
-	DB  08,08,09,11,09,09,12,08,09,12,11,09,10,10,09,10
-	DB  10,10,10,09,11,10,10,12,10,10,11,11,11,10,12,11
-	DB  11,11,00,11,01,02,03,04,03,04,04,05,05,05,06,07
-	DB  12,07,07,07,08,07,08,12,08,08,08,09,08,09,09,09
-	DB  08,09,09,09,09,10,10,09,10,10,10,13,09,13,13,13
-	DB  13,13,10,11,13,11,10,13,11,11,11,11,11,10,10,12
+    db 00,00,00,00,00,02,00,02,02,03,01,02,04,04,03,04
+    db 04,05,04,05,05,02,03,04,06,06,01,06,02,03,06,07
+    db 05,06,07,06,06,06,07,06,04,04,05,06,08,07,06,06
+    db 07,06,08,07,03,04,03,04,04,05,05,05,08,09,09,07
+    db 07,07,08,07,08,08,08,02,08,09,03,05,09,05,08,06
+    db 06,07,06,10,07,09,08,07,08,08,09,08,08,09,08,10
+    db 09,00,08,01,10,02,03,04,04,05,06,10,06,06,06,07
+    db 06,07,07,10,08,08,07,11,11,08,11,08,09,09,09,08
+    db 09,11,09,09,10,10,10,10,10,00,10,09,02,02,04,03
+    db 04,04,11,05,05,11,07,07,07,07,07,08,10,08,08,08
+    db 08,08,09,11,09,09,12,08,09,12,11,09,10,10,09,10
+    db 10,10,10,09,11,10,10,12,10,10,11,11,11,10,12,11
+    db 11,11,00,11,01,02,03,04,03,04,04,05,05,05,06,07
+    db 12,07,07,07,08,07,08,12,08,08,08,09,08,09,09,09
+    db 08,09,09,09,09,10,10,09,10,10,10,13,09,13,13,13
+    db 13,13,10,11,13,11,10,13,11,11,11,11,11,10,10,12
 
-	DB  00,00,00,00,00,00,00,01,01,00,00,00,01,00,02,02
-	DB  03,02,01,04,01,01,01,01,03,04,00,05,01,01,04,01
-	DB  01,00,04,02,03,04,01,05,01,02,01,00,02,06,03,04
-	DB  01,05,06,04,00,00,02,02,03,02,03,04,06,02,03,02
-	DB  03,04,00,05,02,03,04,00,05,00,02,00,03,02,07,01
-	DB  02,00,04,00,03,07,00,05,02,03,08,04,05,00,06,07
-	DB  03,00,07,00,08,01,01,01,02,01,00,09,02,03,04,01
-	DB  05,03,04,07,01,02,06,01,02,05,04,06,02,03,04,07
-	DB  05,07,06,06,00,01,02,03,04,00,05,08,00,01,00,02
-	DB  02,03,00,03,04,03,00,01,02,03,04,00,09,02,03,04
-	DB  04,05,00,08,02,03,00,07,05,03,09,06,00,01,07,03
-	DB  04,04,05,08,10,06,06,08,07,07,00,00,01,08,09,04
-	DB  05,05,00,06,00,00,00,00,02,02,03,02,03,04,03,00
-	DB  01,02,03,04,00,05,02,06,04,04,05,00,06,02,03,04
-	DB  07,05,05,06,06,00,01,07,03,04,04,00,08,02,03,04
-	DB  04,05,07,00,06,01,08,07,04,05,05,06,06,09,09,11
+    db 00,00,00,00,00,00,00,01,01,00,00,00,01,00,02,02
+    db 03,02,01,04,01,01,01,01,03,04,00,05,01,01,04,01
+    db 01,00,04,02,03,04,01,05,01,02,01,00,02,06,03,04
+    db 01,05,06,04,00,00,02,02,03,02,03,04,06,02,03,02
+    db 03,04,00,05,02,03,04,00,05,00,02,00,03,02,07,01
+    db 02,00,04,00,03,07,00,05,02,03,08,04,05,00,06,07
+    db 03,00,07,00,08,01,01,01,02,01,00,09,02,03,04,01
+    db 05,03,04,07,01,02,06,01,02,05,04,06,02,03,04,07
+    db 05,07,06,06,00,01,02,03,04,00,05,08,00,01,00,02
+    db 02,03,00,03,04,03,00,01,02,03,04,00,09,02,03,04
+    db 04,05,00,08,02,03,00,07,05,03,09,06,00,01,07,03
+    db 04,04,05,08,10,06,06,08,07,07,00,00,01,08,09,04
+    db 05,05,00,06,00,00,00,00,02,02,03,02,03,04,03,00
+    db 01,02,03,04,00,05,02,06,04,04,05,00,06,02,03,04
+    db 07,05,05,06,06,00,01,07,03,04,04,00,08,02,03,04
+    db 04,05,07,00,06,01,08,07,04,05,05,06,06,09,09,11
 </pre>
 
 <p>In these values, each block of bytes corresponds to a PSG channel, and each index from 0…255 in one of these blocks bytes corresponds to a sample value point. The total maximum volume you should be able to generate with these is about 30% more than a single channel outputting at maximum volume. The speed can be optimized a little more by aligning the table to a multiple of 256 address, if you need it.</p>

          
M articles/split_guide.php +46 -43
@@ 74,12 74,14 @@ A: I tested the statements made in this 
 <p>Example code to poll for the end of HBLANK, assumes disabled interrupts and s#2 to be set:</p>
 
 <pre>
-Poll_1:	in	a,(#99)		;wait until start of HBLANK
-	and	%00100000
-	jp	nz,Poll_1
-Poll_2:	in	a,(#99)		;wait until end of HBLANK
-	and	%00100000
-	jp	z,Poll_2
+Poll_1:
+    in a,(#99)      ; wait until start of HBLANK
+    and %00100000
+    jp nz,Poll_1
+Poll_2:
+    in a,(#99)      ; wait until end of HBLANK
+    and %00100000
+    jp z,Poll_2
 </pre>
 
 

          
@@ 95,15 97,16 @@ A: The VDP lineinterrupt is linked to the FH bit, and the interrupt occurs when the FH bit is set. The FH bit will be set at the <em>exact</em> beginning of the line in r#19 + 1, so that’s the line <em>after</em> the line set. If register 19 contains the value 99, the lineinterrupt will occur at the utter left of line 100, inside the left border (which is about halfway the horizontal blanking period).</p>
 <p>Example code for polling FH, assumes disabled interrupts and s#1 to be set:</p>
 
 <pre>
-	ld	a,(VDP+23)	;set split line
-	add	a,SPLITLINE
-	out	(#99),a
-	ld	a,19+128
-	out	(#99),a
-	nop			;don’t access too fast
-Poll:	in	a,(#99)		;poll until line reached, also clears FH bit
-	rra
-	jp	nc,Poll
+    ld a,(VDP+23)   ; set split line
+    add a,SPLITLINE
+    out (#99),a
+    ld a,19+128
+    out (#99),a
+    nop             ; don’t access too fast
+Poll:
+    in a,(#99)      ; poll until line reached, also clears FH bit
+    rra
+    jp nc,Poll
 </pre>
 
 <p>Ofcourse, when not using this code in an interrupt routine you shouldn’t keep the interrupts disabled in the polling loop all the time.</p>

          
@@ 134,44 137,44 @@ A: This is in my opinion the best way to have a screensplit. It looks very tidy, it is easy to program and doesn’t require any ‘special’ (read: difficult or processor-dependant) timing. Basically, there will just be a black line at the spot of the split, but you won’t have to put that line in your images, although you ofcourse have to keep it into account when drawing them and designing your screen’s layout.</p>
 
 <pre>
 ;
-;A macro definition which waits until the end of the next/current HBLANK...
+; A macro definition which waits until the end of the next/current HBLANK...
 ;
 Wait_HBLANK:
-	MACRO			;(this macro is Compass-formatted)
+    MACRO           ; (this macro is Compass-formatted)
 WHL1_@sym:
-	in	a,(#99)		;wait until start of HBLANK
-	and	%00100000
-	jp	nz,WHL1_@sym
+    in a,(#99)      ; wait until start of HBLANK
+    and %00100000
+    jp nz,WHL1_@sym
 WHL2_@sym:
-	in	a,(#99)		;wait until end of HBLANK
-	and	%00100000
-	jp	z,WHL2_@sym
+    in a,(#99)      ; wait until end of HBLANK
+    and %00100000
+    jp z,WHL2_@sym
 	ENDM
 
-
 ;
-;The routine performing the screensplit
+; The routine performing the screensplit
 ;
-Split:	ld	a,2
-	out	(#99),a
-	ld	a,15+128
-	out	(#99),a
-	nop
-	Wait_HBLANK
-	ld	a,(VDP+1)	;disable screen (reset bit 6)
-	and	%10111111
-	out	(#99),a
-	ld	a,1+128
-	out	(#99),a
-	nop	
-	Wait_HBLANK
+Split:
+    ld a,2
+    out (#99),a
+    ld a,15+128
+    out (#99),a
+    nop
+    Wait_HBLANK
+    ld a,(VDP+1)    ; disable screen (reset bit 6)
+    and %10111111
+    out (#99),a
+    ld a,1+128
+    out (#99),a
+    nop
+    Wait_HBLANK
 
-	...			;do your split stuff
+    ...             ; do your split stuff
 
-	ld	a,(VDP+1)
-	out	(#99),a
-	ld	a,1+128
-	out	(#99),a
+    ld a,(VDP+1)
+    out (#99),a
+    ld a,1+128
+    out (#99),a
 </pre>
 
 

          
M articles/vdp_tut.php +168 -154
@@ 95,12 95,12 @@ 
 <p>So the actual code with which you change a register’s value will look something like this:</p>
 
 <pre>
-	ld	a,value
-	di
-	out	(#99),a
-	ld	A,regnr+128
-	ei
-	out	(#99),a
+    ld a,value
+    di
+    out (#99),a
+    ld a,regnr + 128
+    ei
+    out (#99),a
 </pre>
 
 <p>Note the <code>DI</code> and the <code>EI</code> instructions inbetween. It is <em>VERY</em> important that you disable the interrupts during the 2 <code>OUT</code>s. This is because the VDP registers are also changed on the interrupt, and if an interrupt were to occur right inbetween these two <code>OUT</code> instructions the results would be unpredictable. The <code>EI</code> is put before the <code>OUT</code> here since the <code>EI</code> has a delay of 1 instruction on the Z80 before it re-enables the interrupts, and if possible one should keep the interrupts disabled as shortly as possible (some interrupts like line interrupts for screensplits or RS232 interrupts need responses as fast as possible).</p>

          
@@ 117,32 117,32 @@ consecutive <code>OUTI</code> or <code>O
 <p>There is also the other method of addressing the registers, which is, as said before, the indirect method. This means that you can specify the register to write to once, and then repeatedly write values, which is about twice as fast. However the register needs to be the same for all values, or it has to be a successive range of registers (indirect register writing supports auto incrementing). Indirect register writing is done by writing the register number to r#17, also specifying whether to auto-increment, and then writing the desired values to port #9B:</p>
 
 <pre>
-                     MSB  7   6   5   4   3   2   1   0  LSB
-                        +---+---+---+---+---+---+---+---+
-   Register #17         |AII| 0 |R5 |R4 |R3 |R2 |R1 |R0 | REGISTER #
-                        +-+-+---+---+---+---+---+---+---+
-                          |-- 1:  Auto increment inhibit
-                          +-- 0:  Auto increment on
+                  MSB  7   6   5   4   3   2   1   0  LSB
+                     +---+---+---+---+---+---+---+---+
+  Register #17       |AII| 0 |R5 |R4 |R3 |R2 |R1 |R0 | REGISTER #
+                     +-+-+---+---+---+---+---+---+---+
+                       |-- 1:  Auto increment inhibit
+                       +-- 0:  Auto increment on
 
-                        +---+---+---+---+---+---+---+---+
-   Port #3              |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | DATA
-                        +---+---+---+---+---+---+---+---+
+                     +---+---+---+---+---+---+---+---+
+  Port #3            |D7 |D6 |D5 |D4 |D3 |D2 |D1 |D0 | DATA
+                     +---+---+---+---+---+---+---+---+
 </pre>
 
 <p>Code example:</p>
 
 <pre>
-	ld	a,regnr		;add +128 for no auto increment
-	di
-	out	(#99),a
-	ld	A,17+128
-	ei
-	out	(#99),a
+    ld a,regnr      ; add +128 for no auto increment
+    di
+    out (#99),a
+    ld a,17 + 128
+    ei
+    out (#99),a
 
-	ld	b,number_of_bytes
-	ld	c,#9B		;you can also write ld bc,#nn9B, which is faster
-	ld	hl,address
-	otir
+    ld b,number_of_bytes
+    ld c,#9B        ; you can also write ld bc,#nn9B, which is faster
+    ld hl,address
+    otir
 </pre>
 
 <p>Note that since VDP programming can be very tight, especially on screensplits, you often need the fastest solution possible. In that case, consider unrolling the <code>OTIR</code> to <code>OUTI</code>s as discussed in the <a href="/articles/fast_loops.php">Fast Loops</a> article.</p>

          
@@ 167,20 167,20 @@ consecutive <code>OUTI</code> or <code>O
 <p>Some example code to read out a status register:</p>
 
 <pre>
-	ld	a,statusregnr
-	di
-	out	(#99),a
-	ld	a,15+128
-	out	(#99),a
-	in	a,(#99)
-	ex	af,af'
-	xor	a		;ld a,0
-	out	(#99),a
-	ld	a,15+128
-	ei
-	out	(#99),a
-	ex	af,af'
-	ret
+    ld a,statusregnr
+    di
+    out (#99),a
+    ld a,15 + 128
+    out (#99),a
+    in a,(#99)
+    ex af,af'
+    xor a           ; ld a,0
+    out (#99),a
+    ld a,15 + 128
+    ei
+    out (#99),a
+    ex af,af'
+    ret
 </pre>
 
 

          
@@ 204,19 204,19 @@ consecutive <code>OUTI</code> or <code>O
 
 
 <pre>
-                     MSB  7   6   5   4   3   2   1   0  LSB
-                        +---+---+---+---+---+---+---+---+
-   Register #14         | 0 | 0 | 0 | 0 | 0 |A16|A15|A14| VRAM access base
-                        +---+---+---+---+---+---+---+---+ address register
+                   MSB  7   6   5   4   3   2   1   0  LSB
+                      +---+---+---+---+---+---+---+---+
+  Register #14        | 0 | 0 | 0 | 0 | 0 |A16|A15|A14| VRAM access base
+                      +---+---+---+---+---+---+---+---+ address register
 
-                     MSB  7   6   5   4   3   2   1   0  LSB
-                        +---+---+---+---+---+---+---+---+
-   Port #1 First byte   |A7 |A6 |A5 |A4 |A3 |A2 |A1 |A0 | VRAM access base
-                        +===+===+===+===+===+===+===+===+ address registers
-           Second byte  | X | X |A13|A12|A11|A10|A9 |A8 |
-                        +-+-+-+-+---+---+---+---+---+---+
-                          0   0:  Read
-                          0   1:  Write
+                   MSB  7   6   5   4   3   2   1   0  LSB
+                      +---+---+---+---+---+---+---+---+
+  Port #1 First byte  |A7 |A6 |A5 |A4 |A3 |A2 |A1 |A0 | VRAM access base
+                      +===+===+===+===+===+===+===+===+ address registers
+         Second byte  | X | X |A13|A12|A11|A10|A9 |A8 |
+                      +-+-+-+-+---+---+---+---+---+---+
+                        0   0:  Read
+                        0   1:  Write
 </pre>
 
 <p>After having done this, you can read or write the data from or to port #98.

          
@@ 241,8 241,8 @@ slower than the <code>OTIR</code> and <c
 cycles), so use the following code in stead (exactly 29 cycles):</p>
 
 <pre>OutiToVram:
-	outi
-	jp nz,OutiToVram
+    outi
+    jp nz,OutiToVram
 </pre>
 
 <p>The V9938 is quite a bit faster, reads and writes only need to be 15 T-states

          
@@ 293,51 293,51 @@ Finally, note that all V9938 timings als
 
 <pre>
 ;
-;Set VDP address counter to write from address AHL (17-bit)
-;Enables the interrupts
+; Set VDP address counter to write from address AHL (17-bit)
+; Enables the interrupts
 ;
 SetVdp_Write:
-	rlc	h
-	rla
-	rlc	h
-	rla
-	srl	h
-	srl	h
-	di
-	out	(#99),a
-	ld	a,14+128
-	out	(#99),a
-	ld	a,l
-	nop
-	out	(#99),a
-	ld	a,h
-	or	64
-	ei
-	out	(#99),a
-	ret
+    rlc h
+    rla
+    rlc h
+    rla
+    srl h
+    srl h
+    di
+    out (#99),a
+    ld a,14 + 128
+    out (#99),a
+    ld a,l
+    nop
+    out (#99),a
+    ld a,h
+    or 64
+    ei
+    out (#99),a
+    ret
 
 ;
-;Set VDP address counter to read from address AHL (17-bit)
-;Enables the interrupts
+; Set VDP address counter to read from address AHL (17-bit)
+; Enables the interrupts
 ;
 SetVdp_Read:
-	rlc	h
-	rla
-	rlc	h
-	rla
-	srl	h
-	srl	h
-	di
-	out	(#99),a
-	ld	a,14+128
-	out	(#99),a
-	ld	a,l
-	nop
-	out	(#99),a
-	ld	a,h
-	ei
-	out	(#99),a
-	ret
+    rlc h
+    rla
+    rlc h
+    rla
+    srl h
+    srl h
+    di
+    out (#99),a
+    ld a,14 + 128
+    out (#99),a
+    ld a,l
+    nop
+    out (#99),a
+    ld a,h
+    ei
+    out (#99),a
+    ret
 </pre>
 
 

          
@@ 361,35 361,47 @@ SetVdp_Read:
 
 <pre>
 ;
-;Fast DoCopy, by Grauw
-;In:  HL = pointer to 15-byte VDP command data
-;Out: HL = updated
+; Fast DoCopy, by Grauw
+; In:  HL = pointer to 15-byte VDP command data
+; Out: HL = updated
 ;
-DoCopy:	ld	a,32
-	di
-	out	(#99),a
-	ld	a,17+128
-	out	(#99),a
-	ld	c,#9B
+DoCopy:
+    ld a,32
+    di
+    out (#99),a
+    ld a,17 + 128
+    out (#99),a
+    ld c,#9B
 VDPready:
-	ld	a,2
-	di
-	out	(#99),a		;select s#2
-	ld	a,15+128
-	out	(#99),a
-	in	a,(#99)
-	rra
-	ld 	a,0		;back to s#0, enable ints
-	out	(#99),a
-	ld	a,15+128
-	ei
-	out	(#99),a		;loop if vdp not ready (CE)
-	jp	c,VDPready
-	DW	#A3ED,#A3ED,#A3ED,#A3ED	  ;15x OUTI
-	DW	#A3ED,#A3ED,#A3ED,#A3ED	  ; (faster than OTIR)
-	DW	#A3ED,#A3ED,#A3ED,#A3ED
-	DW	#A3ED,#A3ED,#A3ED
-	ret
+    ld a,2
+    di
+    out (#99),a     ; select s#2
+    ld a,15 + 128
+    out (#99),a
+    in a,(#99)
+    rra
+    ld a,0          ; back to s#0, enable ints
+    out (#99),a
+    ld a,15 + 128
+    ei
+    out (#99),a     ; loop if vdp not ready (CE)
+    jp c,VDPready
+    outi            ; 15x OUTI
+    outi            ; (faster than OTIR)
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    ret
 </pre>
 
 

          
@@ 402,20 414,20 @@ VDPready:
 
 <pre>
 ;
-;Set the palette to the one HL points to...
-;Modifies: AF, BC, HL (=updated)
-;Enables the interrupts.
+; Set the palette to the one HL points to...
+; Modifies: AF, BC, HL (=updated)
+; Enables the interrupts.
 ;
 SetPalette:
-	xor	a		;Set p#pointer to zero.
-	di
-	out	(#99),a
-	ld	a,16+128
-	ei
-	out	(#99),a
-	ld	bc,#209A	;out 32x to port #9A
-	otir
-	ret
+    xor a           ; set p#pointer to zero.
+    di
+    out (#99),a
+    ld a,16+128
+    ei
+    out (#99),a
+    ld bc,#209A     ; out 32x to port #9A
+    otir
+    ret
 </pre>
 
 

          
@@ 426,40 438,42 @@ SetPalette:
 
 <pre>
 ;
-;Is supposed to run in screen 5, so you should make a small BASIC loader,
+; Is supposed to run in screen 5, so you should make a small BASIC loader,
 ; or call the CHMOD BIOS routine.
 ;
 DoExampleCopy:
-	xor	a		;set vram write base address
-	ld	hl,#8000	; to 1st byte of page 1...
-	call	SetVDP_Write
+    xor a           ; set vram write base address
+    ld hl,#8000     ;  to 1st byte of page 1...
+    call SetVDP_Write
 
-	ld	a,#88		;use color 8 (red)
-FillL1:	ld	c,8		;fill 1st 8 lines of page 1
-FillL2:	ld	b,128		;
-	out	(#98),a		;could also have been done with
-	djnz	FillL2		;a vdp command (probably faster)
-	dec	c		;(and could also use a fast loop)
-	jp	nz,FillL1
+    ld a,#88        ; use color 8 (red)
+FillL1:
+    ld c,8          ; fill 1st 8 lines of page 1
+FillL2:
+    ld b,128        ;
+    out (#98),a     ; could also have been done with
+    djnz FillL2     ; a vdp command (probably faster)
+    dec c           ; (and could also use a fast loop)
+    jp nz,FillL1
 
-	ld	hl,COPYBLOCK	;execute the copy
-	call	DoCopy
+    ld hl,COPYBLOCK ; execute the copy
+    call DoCopy
 
-	ret
+    ret
 
 
 COPYBLOCK:
-	DB	0,0,0,1
-	DB	0,0,0,0
-	DB	8,0,8,0
-	DB	0,0,#D0		;HMMM
+    db 0,0,0,1
+    db 0,0,0,0
+    db 8,0,8,0
+    db 0,0,#D0        ; HMMM
 
-;As an alternate notation, you might actually prefer the following:
+; As an alternate notation, you might actually prefer the following:
 ;
-;	DW	#0000,#0100
-;	DW	#0000,#0000
-;	DW	#0008,#0008
-;	DB	0,0,#D0
+;   dw    #0000,#0100
+;   dw    #0000,#0000
+;   dw    #0008,#0008
+;   db    0,0,#D0
 </pre>
 
 

          
M sources/docopy.php +84 -60
@@ 16,58 16,70 @@ 
 
 <pre>
 ;
-;Fast DoCopy, by Grauw
-;In:  HL = pointer to 15-byte VDP command data
-;Out: HL = updated
+; Fast DoCopy, by Grauw
+; In:  HL = pointer to 15-byte VDP command data
+; Out: HL = updated
 ;
-DoCopy:	ld	a,32
-	di
-	out	(#99),a
-	ld	a,17+128
-	out	(#99),a
-	ld	c,#9B
+DoCopy:
+    ld a,32
+    di
+    out (#99),a
+    ld a,17+128
+    out (#99),a
+    ld c,#9B
 VDPready:
-	ld	a,2
-	di
-	out	(#99),a		;select s#2
-	ld	a,15+128
-	out	(#99),a
-	in	a,(#99)
-	rra
-	ld 	a,0		;back to s#0, enable ints
-	out	(#99),a
-	ld	a,15+128
-	ei
-	out	(#99),a		;loop if vdp not ready (CE)
-	jp	c,VDPready
-	DW	#A3ED,#A3ED,#A3ED,#A3ED	  ;15x OUTI
-	DW	#A3ED,#A3ED,#A3ED,#A3ED	  ; (faster than OTIR)
-	DW	#A3ED,#A3ED,#A3ED,#A3ED
-	DW	#A3ED,#A3ED,#A3ED
-	ret
+    ld a,2
+    di
+    out (#99),a     ; select s#2
+    ld a,15+128
+    out (#99),a
+    in a,(#99)
+    rra
+    ld  a,0         ; back to s#0, enable ints
+    out (#99),a
+    ld a,15+128
+    ei
+    out (#99),a     ; loop if vdp not ready (CE)
+    jp c,VDPready
+    outi            ; 15x OUTI
+    outi            ; (faster than OTIR)
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    ret
 </pre>
 
 <p>I sometimes find this useful too, a separate routine to wait for the VDP to finish its current command.</p>
 
 <pre>
 ;
-;This lil' routine waits until the VDP is done copying.
+; This lil' routine waits until the VDP is done copying.
 ;
 VDP_Ready:
-	ld	a,2
-	di
-	out	(#99),a		;select s#2
-	ld	a,15+128
-	out	(#99),a
-	in	a,(#99)
-	rra
-	ld	a,0		;back to s#0, enable ints
-	out	(#99),a
-	ld	a,15+128
-	ei
-	out	(#99),a		;loop if vdp not ready (CE)
-	jp	c,VDPready
-	ret
+    ld a,2
+    di
+    out (#99),a     ; select s#2
+    ld a,15+128
+    out (#99),a
+    in a,(#99)
+    rra
+    ld a,0          ; back to s#0, enable ints
+    out (#99),a
+    ld a,15+128
+    ei
+    out (#99),a     ; loop if vdp not ready (CE)
+    jp c,VDPready
+    ret
 </pre>
 
 

          
@@ 75,26 87,38 @@ VDP_Ready:
 
 <pre>
 ;
-;Faster again!!! DoCopy, by Grauw
-;In:  HL = pointer to 15-byte VDP command data
-;Out: HL = updated
+; Faster again!!! DoCopy, by Grauw
+; In:  HL = pointer to 15-byte VDP command data
+; Out: HL = updated
 ;
-DoCopy:	ld	a,32
-	di
-	out	(#99),a
-	ld	a,17+128
-	ei
-	out	(#99),a
-	ld	c,#9B
+DoCopy:
+    ld a,32
+    di
+    out (#99),a
+    ld a,17+128
+    ei
+    out (#99),a
+    ld c,#9B
 VDPready:
-	in	a,(#99)		;loop if vdp not ready (CE)
-	rra
-	jp      c,VDPready
-	DW	#A3ED,#A3ED,#A3ED,#A3ED	  ;15x OUTI
-	DW	#A3ED,#A3ED,#A3ED,#A3ED
-	DW	#A3ED,#A3ED,#A3ED,#A3ED
-	DW	#A3ED,#A3ED,#A3ED
-	ret
+    in a,(#99)      ; loop if vdp not ready (CE)
+    rra
+    jp c,VDPready
+    outi            ; 15x OUTI
+    outi            ; (faster than OTIR)
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    outi
+    ret
 
 </pre>
 

          
M sources/load_screen.php +9 -8
@@ 26,7 26,7 @@ Start:        ld      de,FILENAME
               call    LoadScreen
               ret
 
-FILENAME:     DB	"IMAGE.SC5",0
+FILENAME:     DB      "IMAGE.SC5",0
 </pre>
 
 

          
@@ 151,9 151,10 @@ LoadScr_End:
 ;Handle an error...
 ;Returns to DOS 2 which will show the error.
 ;
-Error:	ld	b,a
-	ld	c,_TERM
-	jp	Bdos
+Error:
+    ld b,a
+    ld c,_TERM
+    jp Bdos
 </pre>
 
 

          
@@ 167,21 168,21 @@ Error:	ld	b,a
 ;
 ;DE = filename
 ;
-Load_Palet:   ld      c,_OPEN	;Open File Handle (no flags)
+Load_Palet:   ld      c,_OPEN   ;Open File Handle (no flags)
               xor     a
               call    Bdos
               jp      nz,Error
               push    bc
               ld      de,TEMP1
               ld      hl,32
-              ld      c,_READ	;Read From File Handle
+              ld      c,_READ   ;Read From File Handle
               call    Bdos
               jp      nz,Error
               pop     bc
-              ld      c,_CLOSE	;Close File Handle
+              ld      c,_CLOSE  ;Close File Handle
               call    Bdos
               jp      nz,Error
-              ld      hl,TEMP1	;Set palette
+              ld      hl,TEMP1  ;Set palette
               jp      SetPalet
 </pre>
 

          
M sources/vdp_rout.php +5 -5
@@ 28,9 28,9 @@ INITXT:       equ     #6C
 
 ;
 VDP_SetReg:   MACRO   @register        ;Set value A in the specified register
-              out	(#99),a
-              ld	a,@register+128
-              out	(#99),a
+              out     (#99),a
+              ld      a,@register+128
+              out     (#99),a
               ENDM
 
 

          
@@ 113,7 113,7 @@ Rest_VdpRegs: ld      bc,#0800
               ld      hl,VDP_8
               call    Rest_VdpSub
               ld      bc,#0319
-              ld      hl,TRIPLE_ZERO	;a jp Restore_Vdp_Sub is implied
+              ld      hl,TRIPLE_ZERO     ;a jp Restore_Vdp_Sub is implied
 Rest_VdpSub:  ld      a,(hl)
               inc     hl
               di

          
@@ 134,7 134,7 @@ TRIPLE_ZERO:  DB      0,0,0
 ;
 ;Selecteer screen 5...
 ;
-Screen5:      ld      a,(VDP)	         ;Select screen 5 (0)
+Screen5:      ld      a,(VDP)            ;Select screen 5 (0)
               and     %11110001
               or      %00000110
               ld      (VDP),a