Fixed compile warnings.
M jasm/assemble/assembler_impl/assembler_impl.cpp +4 -0
@@ 21,6 21,10 @@ namespace jasm {
 
 using namespace core;
 
+RangedLoopContainer::~RangedLoopContainer()
+{
+}
+
 Assembler::Assembler(
 	  bool multiple_output_files
 	, bool multi_bank_mode

          
M jasm/assemble/assembler_impl/assembler_impl.h +1 -0
@@ 58,6 58,7 @@ constexpr uint32_t max_call_depth = 100;
 class RangedLoopContainer
 {
 public:
+	virtual ~RangedLoopContainer();
 	virtual size_t size() const = 0;
 	virtual const Value &operator[](size_t index) = 0;
 };

          
M jasm/pch.h +2 -0
@@ 10,6 10,8 @@ 
 	#pragma clang diagnostic ignored "-Wmissing-variable-declarations"
 	#pragma clang diagnostic ignored "-Wpadded"
 	#pragma clang diagnostic ignored "-Wfloat-equal"
+	#pragma clang diagnostic ignored "-Wswitch-default"
+	#pragma clang diagnostic ignored "-Wunsafe-buffer-usage"
 	#define DECLARE_SWITCH_FALLTHROUGH [[clang::fallthrough]];
 #else
 	#define DECLARE_SWITCH_FALLTHROUGH

          
M jasm/processor/45gs02/instructions_45gs02.cpp +6 -1
@@ 58,6 58,9 @@ constexpr OpCode op(uint8_t op1, uint8_t
 }
 
 uint32_t __addressing_modes_mask[static_cast<int>(InstructionType::NumTypes)] = {
+#define __ xx
+#define ___ xxx
+#define ____ xxxx
 	/*        Bp   Abs   Bpx   AbsX   Bpy   AbsY   BpIX   IndX   Rel   RelW   BInd   Ind   BpIY   BpIZ | BIQ | BIQZ   SpIY   Imp   Imm   ImmW   Bb   Bbr */
 	/* ADC */ Bp | Abs | Bpx | AbsX | ___ | AbsY | BpIX | ____ | ___ | ____ | ____ | ___ | BpIY | BpIZ | ___ | BIQZ | ____ | ___ | Imm | ____ | __ | ___ ,
 	/* ADCQ*/ Bp | Abs | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | BInd | ___ | ____ | ____ | BIQ | ____ | ____ | ___ | ___ | ____ | __ | ___ ,

          
@@ 195,7 198,9 @@ uint32_t __addressing_modes_mask[static_
 	/* BRA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ ,
 	/* DEA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | Imp | ___ | ____ | __ | ___ ,
 	/* INA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | Imp | ___ | ____ | __ | ___ ,
-
+#undef __
+#undef ___
+#undef ____
 };
 
 OpCodes __opcodes[static_cast<int>(InstructionType::NumTypes)] = {

          
M jasm/processor/45gs02/instructions_45gs02.h +3 -3
@@ 191,9 191,9 @@ namespace AddressingModeMask
 		Bb = 1 << static_cast<int>(AddressingModeType::BitBp),
 		Bbr = 1 << static_cast<int>(AddressingModeType::BitBpRel),
 		
-		__ = 0,
-		___ = 0,
-		____ = 0,
+		xx = 0,
+		xxx = 0,
+		xxxx = 0,
 	};
 }
 

          
M jasm/processor/6502/instructions_6502.cpp +6 -1
@@ 16,6 16,9 @@ struct OpCodes
 };
 
 uint16_t __addressing_modes_mask[static_cast<int>(InstructionType::NumTypes)] = {
+#define __ xx
+#define ___ xxx
+#define ____ xxxx
 	/* ADC */ ___ | Imm | Zp | Zpx | ___ | Abs | AbsX | AbsY | ___ | ___ | IndX | IndY ,
 	/* AND */ ___ | Imm | Zp | Zpx | ___ | Abs | AbsX | AbsY | ___ | ___ | IndX | IndY ,
 	/* ASL */ Imp | ___ | Zp | Zpx | ___ | Abs | AbsX | ____ | ___ | ___ | ____ | ____ ,

          
@@ 75,7 78,9 @@ uint16_t __addressing_modes_mask[static_
 
 	/* BHS */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ ,
 	/* BLT */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ ,
-
+#undef __
+#undef ___
+#undef ____
 };
 
 OpCodes __opcodes[static_cast<int>(InstructionType::NumTypes)] = {

          
M jasm/processor/6502/instructions_6502.h +3 -3
@@ 114,9 114,9 @@ namespace AddressingModeMask
 		Ind = 1 << static_cast<int>(AddressingModeType::IndirectAddr),
 		IndX = 1 << static_cast<int>(AddressingModeType::IndirectIndexX),
 		IndY = 1 << static_cast<int>(AddressingModeType::IndirectIndexY),
-		__ = 0,
-		___ = 0,
-		____ = 0,
+		xx = 0,
+		xxx = 0,
+		xxxx = 0,
 	};
 }
 

          
M jasm/processor/65c02/instructions_65c02.cpp +6 -1
@@ 16,6 16,9 @@ struct OpCodes
 };
 
 uint16_t __addressing_modes_mask[static_cast<int>(InstructionType::NumTypes)] = {
+#define __ xx
+#define ___ xxx
+#define ____ xxxx
 	/* ADC */ Zp | Abs | Zpx | AbsX | ___ | AbsY | ZpI | ___ | ZpIX | ____ | ZpIY | ___ | Imm | __ | ___ | ___ ,
 	/* AND */ Zp | Abs | Zpx | AbsX | ___ | AbsY | ZpI | ___ | ZpIX | ____ | ZpIY | ___ | Imm | __ | ___ | ___ ,
 	/* ASL */ Zp | Abs | Zpx | AbsX | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | ___ | __ | ___ | ___ ,

          
@@ 91,7 94,9 @@ uint16_t __addressing_modes_mask[static_
 	/* BLT */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel ,
 	/* DEA */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | ___ | __ | ___ | ___ ,
 	/* INA */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | ___ | __ | ___ | ___ ,
-
+#undef __
+#undef ___
+#undef ____
 };
 
 OpCodes __opcodes[static_cast<int>(InstructionType::NumTypes)] = {

          
M jasm/processor/65c02/instructions_65c02.h +3 -3
@@ 140,9 140,9 @@ namespace AddressingModeMask
 		Bz = 1 << static_cast<int>(AddressingModeType::BitZp),
 		Bzr = 1 << static_cast<int>(AddressingModeType::BitZpRel),
 		Rel = 1 << static_cast<int>(AddressingModeType::RelativeAddr),
-		__ = 0,
-		___ = 0,
-		____ = 0,
+		xx = 0,
+		xxx = 0,
+		xxxx = 0,
 	};
 }
 

          
M jasm/processor/65ce02/instructions_65ce02.cpp +6 -1
@@ 16,6 16,9 @@ struct OpCodes
 };
 
 uint32_t __addressing_modes_mask[static_cast<int>(InstructionType::NumTypes)] = {
+#define __ xx
+#define ___ xxx
+#define ____ xxxx
 	/*        Bp   Abs   Bpx   AbsX   Bpy   AbsY   BpIX   IndX   Rel   RelW   BpIY   BpIZ   SpIY   Ind   Imp   Imm   ImmW   Bb   Bbr */
 	/* ADC */ Bp | Abs | Bpx | AbsX | ___ | AbsY | BpIX | ____ | ___ | ____ | BpIY | BpIZ | ____ | ___ | ___ | Imm | ____ | __ | ___ ,
 	/* AND */ Bp | Abs | Bpx | AbsX | ___ | AbsY | BpIX | ____ | ___ | ____ | BpIY | BpIZ | ____ | ___ | ___ | Imm | ____ | __ | ___ ,

          
@@ 114,7 117,9 @@ uint32_t __addressing_modes_mask[static_
 	/* BRA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ ,
 	/* DEA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ____ | ____ | ___ | Imp | ___ | ____ | __ | ___ ,
 	/* INA */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ____ | ____ | ___ | Imp | ___ | ____ | __ | ___ ,
-
+#undef __
+#undef ___
+#undef ____
 };
 
 OpCodes __opcodes[static_cast<int>(InstructionType::NumTypes)] = {

          
M jasm/processor/65ce02/instructions_65ce02.h +3 -3
@@ 168,9 168,9 @@ namespace AddressingModeMask
 		Bb = 1 << static_cast<int>(AddressingModeType::BitBp),
 		Bbr = 1 << static_cast<int>(AddressingModeType::BitBpRel),
 		
-		__ = 0,
-		___ = 0,
-		____ = 0,
+		xx = 0,
+		xxx = 0,
+		xxxx = 0,
 	};
 }