Added optional immediate argument to BRK instruction on 6502-alike CPU's.
10 files changed, 19 insertions(+), 5 deletions(-) M jasm/docs/jasm.md M jasm/processor/45gs02/instructions_45gs02.cpp M jasm/processor/6502/instructions_6502.cpp M jasm/processor/65c02/instructions_65c02.cpp M jasm/processor/65ce02/instructions_65ce02.cpp M jasm/unit_tests/results/test_all_instructions_45gs02.bin M jasm/unit_tests/results/test_all_instructions_6502.bin M jasm/unit_tests/test_all_instructions_45gs02.asm M jasm/unit_tests/test_all_instructions_6502.asm M jasm/website/site/docs/index.html
M jasm/docs/jasm.md +6 -0
@@ 130,6 130,12 @@ jAsm supports all regular instructions o lda #0 sta $d020 +The `[6502]|brk` instruction takes an optional immediate argument since `[6502]|rti` actually will return to the instruction after that argument (this goes for 65C02, 65CE02 and 45GS02 as well). + + [6502] + brk // valid but rti won't return directly after this instruction + brk #0 // optional argument makes rti return to next instruction + Due to the large amount of source code with upper case instruction keywords, a python script is provided to convert upper case keywords in all .asm files in a directory. Run that like this. [text]
M jasm/processor/45gs02/instructions_45gs02.cpp +2 -2
@@ 81,7 81,7 @@ uint32_t __addressing_modes_mask[static_ /* BMI */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ , /* BNE */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ , /* BPL */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ , - /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | Imp | ___ | ____ | __ | ___ , + /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ____ | ____ | Imp | Imm | ____ | __ | ___ , /* Bp Abs Bpx AbsX Bpy AbsY BpIX IndX Rel RelW BInd Ind BpIY BpIZ | BIQ | BIQZ SpIY Imp Imm ImmW Bb Bbr */ /* BRU */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ , /* BSR */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | RelW | ____ | ___ | ____ | ____ | ___ | ____ | ____ | ___ | ___ | ____ | __ | ___ , @@ 257,7 257,7 @@ OpCodes __opcodes[static_cast<int>(Instr /* BPL */ {{op(), op(), op(), op(), op(), op(), op(), op(), op(0x10), op(0x13), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op()}}, /* BP, ABSO, BPX, ABSX, BPY, ABSY, BPIX, INDX, RELA, RELW, BIND, INDI, BPIY, BPIZ, BIQ, BIQZ, SPIY, IMPL, IMME, IMMW, BB, BBR,*/ - /* BRK */ {{op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(0x00), op(), op(), op(), op()}}, + /* BRK */ {{op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(0x00), op(0x00), op(), op(), op()}}, /* BP, ABSO, BPX, ABSX, BPY, ABSY, BPIX, INDX, RELA, RELW, BIND, INDI, BPIY, BPIZ, BIQ, BIQZ, SPIY, IMPL, IMME, IMMW, BB, BBR,*/ /* BRU */ {{op(), op(), op(), op(), op(), op(), op(), op(), op(0x80), op(0x83), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op(), op()}},
M jasm/processor/6502/instructions_6502.cpp +1 -1
@@ 26,7 26,7 @@ uint16_t __addressing_modes_mask[static_ /* BMI */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ , /* BNE */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ , /* BPL */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ , - /* BRK */ Imp | ___ | __ | ___ | ___ | ___ | ____ | ____ | ___ | ___ | ____ | ____ , + /* BRK */ Imp | Imm | __ | ___ | ___ | ___ | ____ | ____ | ___ | ___ | ____ | ____ , /* BVC */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ , /* BVS */ ___ | ___ | __ | ___ | ___ | ___ | ____ | ____ | Rel | ___ | ____ | ____ , /* CLC */ Imp | ___ | __ | ___ | ___ | ___ | ____ | ____ | ___ | ___ | ____ | ____ ,
M jasm/processor/65c02/instructions_65c02.cpp +1 -1
@@ 29,7 29,7 @@ uint16_t __addressing_modes_mask[static_ /* BNE */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel , /* BPL */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel , /* BRA */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel , - /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | ___ | __ | ___ | ___ , + /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | Imm | __ | ___ | ___ , /* BVC */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel , /* BVS */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | ___ | ___ | __ | ___ | Rel , /* CLC */ __ | ___ | ___ | ____ | ___ | ____ | ___ | ___ | ____ | ____ | ____ | Imp | ___ | __ | ___ | ___ ,
M jasm/processor/65ce02/instructions_65ce02.cpp +1 -1
@@ 31,7 31,7 @@ uint32_t __addressing_modes_mask[static_ /* BMI */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ , /* BNE */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ , /* BPL */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ , - /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ____ | ____ | ___ | Imp | ___ | ____ | __ | ___ , + /* BRK */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | ____ | ____ | ____ | ____ | ___ | Imp | Imm | ____ | __ | ___ , /* BRU */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ , /* BSR */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | ___ | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ , /* BVC */ __ | ___ | ___ | ____ | ___ | ____ | ____ | ____ | Rel | RelW | ____ | ____ | ____ | ___ | ___ | ___ | ____ | __ | ___ ,
M jasm/unit_tests/results/test_all_instructions_45gs02.bin +0 -0
M jasm/unit_tests/results/test_all_instructions_6502.bin +0 -0
M jasm/unit_tests/test_all_instructions_45gs02.asm +1 -0
M jasm/unit_tests/test_all_instructions_6502.asm +1 -0
M jasm/website/site/docs/index.html +6 -0
@@ 165,6 165,12 @@ <span class="instruction">sta</span> <span class="literal">$d020</span> </code></pre> +<p>The <code><span class="instruction">brk</span></code> instruction takes an optional immediate argument since <code><span class="instruction">rti</span></code> actually will return to the instruction after that argument (this goes for 65C02, 65CE02 and 45GS02 as well).</p> + +<pre><code><span class="instruction">brk</span> <span class="comment">// valid but rti won't return directly after this instruction</span> +<span class="instruction">brk</span> <span class="operator">#</span><span class="literal">0</span> <span class="comment">// optional argument makes rti return to next instruction</span> +</code></pre> + <p>Due to the large amount of source code with upper case instruction keywords, a python script is provided to convert upper case keywords in all .asm files in a directory. Run that like this.</p> <pre><code>python3 tools/convert_6502_keyword_case.py <my_source_directory>